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copyright ? cirrus logic, inc. 2009 (all rights reserved) http://www.cirrus.com preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 24-bit, 192-khz, asynchronous sample rate converter with integrated digital audio interface receiver sample rate converter features ? 140 db dynamic range ? -120 db thd+n ? no external master clock required ? supports sample rates up to 211 khz ? input/output sample rate ratios from 6:1 to 1:6 ? master mode master clock/sample rate ratio support: 64, 96, 128, 192, 256, 384, 512, 768, 1024 ? 16-, 18-, 20-, or 24-bit data i/o ? dither automatically applied and scaled to output resolution ? multiple device outputs are phase matched digital audio interface receiver features ? complete eiaj cp1201, iec-60958, aes3, s/pdif compatible receiver ? 28 khz to 216 khz sample rate range ? 2:1 differential aes3 or 4:1 s/pdif input mux ? de-emphasis filtering for 32 khz, 44.1 khz, and 48 khz ? recovered master clock output: 64 x fs, 96 x fs, 128 x fs, 192 x fs, 256 x fs, 384 x fs, 512 x fs, 768 x fs, 1024 x fs ? 49.152 mhz maximum recovered master clock frequency ? ultra-low-jitter clock recovery ? high input jitter tolerance ? no external pll filter components required ? selectable and automatic clock switching ? aes3 direct output and aes3 tx pass- through ? on-chip channel status data buffering ? automatic detection of compressed audio streams ? decodes cd q sub-code serial audio input 4:1 mux rx0/rxp0 rx1/rxn0 rx2/rxp1 rx3/rxn1 receiver clock & data recovery (pll) ilrck isclk sdin sample rate converter c or u data buffer (first 5 bytes) control port & registers 2:1 mux serial audio output 3:1 mux xti clock generator sda/ cdout scl/ cclk ad1/ cdin ad0/ cs rmck general purpose outputs gpo0 format detect gpo1 gpo2 gpo3 olrck1 osclk1 sdout1 tdm_in serial audio output 3:1 mux olrck2 osclk2 sdout2 vl va agnd xto level translators level translators dgnd v_reg may '09 ds692pp2 CS8422
2 ds692pp2 CS8422 system features ? spi ? or i2c ? software mode and stand-alone hardware mode ? flexible 3-wire digital serial audio input port ? dual serial audio output ports with independently selectable data paths ? master or slave mode operation for all serial audio ports ? time division multiplexing (tdm) mode ? integrated oscillator for use with external crystal ? four general-purpose output pins (gpo) ? +3.3 v analog supply (va) ? +1.8 v to 5.0 v digital interface (vl) ? space-saving 32-pin qfn package general description the CS8422 is a 24-bit, high-performance, monolithic cmos stereo asynchronous sample rate converter with an integrated digital audio in terface receiver that de- codes audio data according to the eiaj cp1201, iec- 60958, aes3, and s/pdif interface standards. audio data is input through the digital interface receiver or a 3-wire serial audio input port. audio is output through one of two 3-wire serial audio output ports. se- rial audio data outputs can be set to 24-, 20-, 18-, or 16- bit word-lengths. data into the digital interface receiver and serial audio input port can be up to 24-bits long. in- put and output data can be completely asynchronous, synchronous to an external clock through xti, or syn- chronous to the recovered master clock. the CS8422 can be controlled through the control port in software mode or in a stand-alone hardware mode. in software mode, the user can control the device through an spi or i2c control port. target applications inclu de digital recording systems (dvd-r/rw, cd-r/rw, pvr, dat, md, and vtr), dig- ital mixing consoles, high-quality d/a, effects processors, computer audio systems, and automotive audio systems. the CS8422 is available in a space-saving qfn pack- age in both commercial (-40 c to +85 c) and automotive (-40 c to +105 c) grades. the cdb4822 is also available for device evaluation and implementa- tion suggestions. please refer to ?ordering information? on page 80 for complete details.
ds692pp2 3 CS8422 table of contents 1. pin description ............................................................................................................ ..................... 9 1.1 software mode ............................................................................................................. .................... 9 1.2 hardware mode ............................................................................................................. ................ 11 2. characteristics and specificatio ns .......... ................. ................ ................ ................ ......... 13 recommended operating conditions .................................................................................. 13 absolute maximum rating s ............... ................. ................ ................ ............. ............. ............ 13 performance specifications - sample rate co nverter ........ ................ ............. ......... 14 digital filter characteristics .............................................................................................. 1 4 dc electrical characteristics .............................................................................................. 15 digital interface specifications ........................................................................................... 16 switching specifications ...................................................................................................... ... 17 switching characteristics - control port - spi mode ................................................. 20 switching characteristics - control port - i2c mode .................................................. 21 3. typical connection diagrams ................................................................................................ .22 3.1 software mode ............................................................................................................ .................. 22 3.2 hardware mode ............................................................................................................ ................ 23 4. overview ................................................................................................................... ........................ 24 5. three-wire serial input/output audio port ...................................................................... 24 5.1 serial port clock operation ............................................................................................... ............ 25 5.1.1 master mode ............................................................................................................. ............ 25 5.1.2 slave mode .............................................................................................................. ............. 25 5.1.3 hardware mode control . .................................................................................................. ..... 25 5.1.4 software mode control ................................................................................................... ....... 25 5.1.5 time division multiplexing (tdm) mode ................................................................................ 27 5.1.5.1 tdm master mode ..................................................................................................... 27 5.1.5.2 tdm slave mode ....................................................................................................... 2 7 5.1.5.3 hardware mode control ............................................................................................. 27 5.1.5.4 software mode control .............................................................................................. 27 6. digital interface receiver ................................................................................................. ...... 29 6.1 aes3 and s/pdif standards .. ................ ................. ................ ................ ................ .............. ........ 29 6.2 receiver input multiplexer ................................................................................................ ............. 29 6.2.1 hardware mode control . .................................................................................................. ..... 29 6.2.2 software mode control ................................................................................................... ....... 29 6.2.2.1 single-ended input mode .......................................................................................... 30 6.2.2.2 differential input mode ............................................................................................... 30 6.3 recovered master clock - rmck ............................................................................................. ..... 31 6.3.1 hardware mode control . .................................................................................................. ..... 31 6.3.2 software mode control ................................................................................................... ....... 31 6.4 xti system clock mode ..................................................................................................... ........... 31 6.4.1 hardware mode control . .................................................................................................. ..... 32 6.4.2 software mode control ................................................................................................... ....... 32 6.5 aes11 behavior ...... ................ ................ ................. ................ ............. ............. ........... ................. 32 6.6 error and status reporting ................................................................................................ ............ 32 6.6.1 software mode ........................................................................................................... ........... 32 6.6.2 hardware mode control . .................................................................................................. ..... 33 6.7 non-audio detection ....................................................................................................... ............... 33 6.7.1 hardware mode control . .................................................................................................. ..... 34 6.7.2 software mode control ................................................................................................... ....... 34 6.8 format detection (software mode only) .......... ........................................................................... .. 34 6.9 interrupts (software mode only) ................. .......................................................................... ......... 34 6.10 channel status and user data handling .................................................................................... .34 6.10.1 hardware mode control ... ............................................................................................... .... 34
4 ds692pp2 CS8422 6.10.2 software mode control . ................................................................................................. ...... 34 7. sample rate converter (src) ................................................................................................ .. 37 7.1 src data resolution and dither ................... ......................................................................... ....... 37 7.1.1 hardware mode cont rol ................................................................................................... ..... 37 7.1.2 software mode control ................................................................................................... ....... 37 7.2 src locking ............................................................................................................... ................... 37 7.3 src muting ................................................................................................................ .................... 38 7.4 src master clock .......................................................................................................... ............... 38 7.4.1 hardware mode cont rol ................................................................................................... ..... 39 7.4.2 software mode control ................................................................................................... ....... 39 8. hardware mode control ...................................................................................................... .... 39 8.1 hardware mode serial audio port control ................................................................................... .. 40 9. software mode control ...................................................................................................... ..... 42 9.1 control port description ................................................................................................. ............... 42 9.1.1 spi mode ................................................................................................................ ............... 42 9.1.2 i2c mode ................................................................................................................ ................ 43 9.1.3 memory address pointer (m ap) ............................................................................................ 43 10. register quick reference .................................................................................................. .... 44 11. software register bit definitions ...................................................................................... 47 11.1 CS8422 i.d. and version register (01h) ................................................................................... .. 47 11.2 clock control (02h) ...................................................................................................... ................ 47 11.3 receiver input control (03h) ................. ............................................................................ ........... 48 11.4 receiver data control (0 4h) .............................................................................................. .......... 48 11.5 gpo control 1 (05h) ...................................................................................................... .............. 50 11.6 gpo control 2 (06h) ...................................................................................................... .............. 50 11.7 serial audio input clock control (07h) .................................................................................. ...... 50 11.8 src output serial port clo ck control (08h) .............................................................................. .51 11.9 recovered master clock ratio control & misc. (09h) ................................................................ 52 11.10 data routing control(0ah) ............................................................................................... .......... 52 11.11 serial audio input data format (0bh) .... ............................................................................... .... 53 11.12 serial audio output data format - sdout1 (0ch) ................ ................................................... 54 11.13 serial audio output data fo rmat - sdout2 (0dh) .................................................................. 55 11.14 receiver error unmasking (0eh) ......................................................................................... ..... 56 11.15 interrupt unmasking (0fh) ............................................................................................... .......... 56 11.16 interrupt mode (10h) .................................................................................................... .............. 57 11.17 receiver channel status (11h) .......................................................................................... ....... 57 11.18 format detect status (1 2h) .............................................................................................. .......... 58 11.19 receiver error (13h) ................................................................................................... .............. 58 11.20 interrupt status (14h) ................................................................................................. ............... 59 11.21 pll status (15h) ....................................................................................................... ................ 60 11.22 receiver status (16h) .................................................................................................. ............. 61 11.23 fs/xti ratio (17h - 18h) ............................................................................................... ............ 62 11.24 q-channel subcode (19h - 22h) ........................................................................................... ..... 62 11.25 channel status registers (23h - 2ch) .................................................................................... ... 62 11.26 iec61937 pc/pd burst preamble (2dh - 30h) .......................................................................... 63 12. applications .............................................................................................................. ................... 64 12.1 reset, power down, and star t-up .......................................................................................... ..... 64 12.2 power supply, grounding, and pcb layout .... ............................................................................. 6 4 12.3 external receiver components ............................................................................................. ...... 64 12.3.1 attenuating input signals ..................... ......................................................................... ....... 65 12.3.2 isolating transformer requ irements ................................................................................... 66 12.4 channel status buffer management ............... .......................................................................... ... 66 12.4.1 aes3 channel status (c) bit management .. ...................................................................... 66 12.4.2 accessing the e buffer ................................................................................................. ....... 67
ds692pp2 5 CS8422 12.4.3 serial copy management system (scms) ... ...................................................................... 68 12.5 jitter attenuation ................................ ....................................................................... ................... 68 12.6 jitter tolerance ........ ................................................................................................. ................... 69 12.7 group delay .............................................................................................................. ................... 69 13. performance plots ......................................................................................................... .......... 70 14. package dimensions ........................................................................................................ .......... 79 15. thermal characteristics and specifications .............................................................. 79 16. ordering information ...................................................................................................... ........ 80 17. references ................................................................................................................ .................... 80 18. revision history .......................................................................................................... ................ 81
6 ds692pp2 CS8422 list of figures figure 1.non-tdm slave mode timing ............................................................................................ ......... 19 figure 2.tdm slave mode timing ................................................................................................ ............ 19 figure 3.non-tdm master mode timing ........................................................................................... ........ 19 figure 4.tdm master mode timing ............................................................................................... ........... 19 figure 5.spi mode timing ...................................................................................................... .................. 20 figure 6.i2c mode timing ...................................................................................................... ................... 21 figure 7.typical connection diagram, software mo de ............................................................................ .22 figure 8.typical connection diagram, hardware mode ........................................................................... 2 3 figure 9.serial audio interface format ? i2s .................................................................................. ........... 26 figure 10.serial audio interface format ? left-justified ...................................................................... ..... 26 figure 11.serial audio interface fo rmat ? right-justified (master mode only) ........................................ 26 figure 12.serial audio in terface format ? aes3 direct output .......... ................ ................ ............. ......... 26 figure 13.tdm master m ode timing diagram ...................................................................................... .... 28 figure 14.tdm slave mode timing diagram ......... .............................................................................. ..... 28 figure 15.tdm mode configuration (all CS8422 outputs are slave) ........................................................ 28 figure 16.tdm mode configuration (f irst CS8422 output is master, all others are slave) ....................... 28 figure 17.single-ended receiver i nput structure, receiver mode 1 ....................................................... 30 figure 18.differential receiver input structure ............................................................................... .......... 31 figure 19.c/u data outputs .................................................................................................... .................. 36 figure 20.typical connection diagram for crystal cir cuit ...................................................................... .. 38 figure 21.hardware mode clock r outing ......................................................................................... ........ 39 figure 22.control port timing in spi mode ....... .............................................................................. ......... 42 figure 23.control port timing, i2 c slave mode write ........................................................................... .... 43 figure 24.control port timing, i2 c slave mode read ............................................................................ ... 43 figure 25.de-emphasis filter response ......................................................................................... ......... 49 figure 26.professional input circu it - differential mode ...................................................................... ...... 65 figure 27.transformerless pr ofessional input circuit - differential mode ................................................. 65 figure 28.s/pdif mux input circuit, single-ended receiver mode 1 single-ended input circuit ? differential mode ............................................................................................................. .......................... 65 figure 29.s/pdif mux input circuit ? digital mode ............................................................................. .... 65 figure 30.ttl/cmos input circuit ? differential mode .......................................................................... .. 65 figure 31.receiver input attenuat ion ? single-ended input ..................................................................... 66 figure 32.receiver input attenuat ion ? differential input ................ ..................................................... .... 66 figure 33.channel status data buffer structure ................................................................................ ....... 67 figure 34.flowchart for reading the e buffer .................................................................................. ......... 67 figure 35.CS8422 pll jitter attenuation characteristics ....................................................................... .. 68 figure 36.jitter tolerance temp late ........................................................................................... .............. 69 figure 37.wideband fft ? 0 dbfs 1 khz tone, 48 khz:48 khz .......... ................ ............. ............. ......... 70 figure 38.wideband fft ? 0 dbfs 1 khz tone, 44.1 khz:192 khz .. ................ ................ ............. ......... 70 figure 39.wideband fft ? 0 dbfs 1 khz tone, 44.1 khz:48 khz .... ................ ................ ............. ......... 70 figure 40.wideband fft ? 0 dbfs 1 khz tone, 48 khz:44.1 khz .... ................ ................ ............. ......... 70 figure 41.wideband fft ? 0 dbfs 1 khz tone, 48 khz:96 khz .......... ................ ............. ............. ......... 70 figure 42.wideband fft ? 0 dbfs 1 khz tone, 96 khz:48 khz .......... ................ ............. ............. ......... 70 figure 43.wideband fft ? 0 dbfs 1 khz tone, 192 khz:48 khz ..... ................ ................ ............. ......... 71 figure 44.wideband fft ? -60 dbfs 1 khz tone, 48 khz:96 khz .......... ............. ............. ............. ......... 71 figure 45.wideband fft ? -60 dbfs 1 khz tone, 48 khz:48 khz .......... ............. ............. ............. ......... 71 figure 46.wideband fft ? -60 dbfs 1 khz tone, 44.1 khz:192 khz ............... ................ ............. ......... 71 figure 47.wideband fft ? -60 dbfs 1 khz tone, 44.1 khz:48 khz ....... ............. ............. ............. ......... 71 figure 48.wideband fft ? -60 dbfs 1 khz tone, 48 khz:44.1 khz ....... ............. ............. ............. ......... 71 figure 49.wideband fft ? -60 dbfs 1 khz tone, 96 khz:48 khz .......... ............. ............. ............. ......... 72 figure 50.imd ? 10 khz and 11 khz -7 dbfs, 96 khz:48 khz ................................................................. 72 figure 51.wideband fft ? -60 dbfs 1 khz tone, 192 khz:48 khz ........... ................. ................ ............ 72
ds692pp2 7 CS8422 figure 52.imd ? 10 khz and 11 khz -7 dbfs, 48 khz:44.1 khz .............................................................. 72 figure 53.imd ? 10 khz and 11 khz -7 dbfs, 44.1 khz:48 khz .............................................................. 72 figure 54.wideband fft ? 0 dbfs 20 khz tone, 44.1 khz:48 khz ........................................................ 72 figure 55.wideband fft ? 0 dbfs 80 khz tone, 192 khz:192 khz ....................................................... 73 figure 56.wideband fft ? 0 dbfs 20 khz tone, 48 khz:96 khz ........................................................... 73 figure 57.wideband fft ? 0 dbfs 20 khz tone, 48 khz:48 khz ........................................................... 73 figure 58.wideband fft ? 0 dbfs 20 khz tone, 96 khz:48 khz ........................................................... 73 figure 59.wideband fft ? 0 dbfs 20 khz tone, 48 khz:44.1 khz ........................................................ 73 figure 60.thd+n vs. output sample rate ? 0 dbfs 1 khz tone, fsi = 192 khz ................................... 73 figure 61.thd+n vs. output sample rate ? 0 dbfs 1 khz tone, fsi = 48 khz ..................................... 74 figure 62.thd+n vs. output sample rate ? 0 dbfs 1 khz tone, fsi = 96 khz ..................................... 74 figure 63.thd+n vs. output sample rate ? 0 dbfs 1 khz tone, fsi = 44.1 khz .................................. 74 figure 64.dynamic range vs. output sample rate ? -60 dbfs 1 khz tone, fsi = 192 khz ................... 74 figure 65.thd+n vs. output sample rate ? 0 dbfs 1 khz tone, fsi = 32 khz ..................................... 74 figure 66.dynamic range vs. output sample rate ? -60 dbfs 1 khz tone, fsi = 32 khz ..................... 74 figure 67.dynamic range vs. output sample rate ? -60 dbfs 1 khz tone, fsi = 96 khz ..................... 75 figure 68.dynamic range vs. output sample rate ? -60 dbfs 1 khz tone, fsi = 44.1 khz .................. 75 figure 69.frequency response ? 0 dbfs input .................................................................................... ... 75 figure 70.passband ripple - 192 khz:48 khz ...................................................................................... .... 75 figure 71.dynamic range vs. output sample rate ? -60 dbfs 1 khz tone, fsi = 48 khz ..................... 75 figure 72.linea rity error ? 0 to -140 dbfs input, 200 hz tone, 48 khz:48 khz ...................................... 75 figure 73.linea rity error ? 0 to -140 dbfs input, 200 hz tone, 48 khz:44.1 khz ................................... 76 figure 74.linea rity error ? 0 to -140 dbfs input, 200 hz tone, 48 khz:96 khz ...................................... 76 figure 75.linea rity error ? 0 to -140 dbfs input, 200 hz tone, 96 khz:48 khz ...................................... 76 figure 76.linearity error ? 0 to -140 dbfs input, 200 hz tone, 44.1 khz:192 khz ................................. 76 figure 77.linea rity error ? 0 to -140 dbfs input, 200 hz tone, 44.1 khz:48 khz ................................... 76 figure 78.linearity error ? 0 to -140 dbfs input, 200 hz tone, 192 khz:44.1 khz ................................. 76 figure 79.thd+n vs. input amplitude ? 1 khz tone, 48 khz:44.1 khz ................................................... 77 figure 80.thd+n vs. input amplitude ? 1 khz tone, 48 khz:96 khz ...................................................... 77 figure 81.thd+n vs. input amplitude ? 1 khz tone, 96 khz:48 khz ...................................................... 77 figure 82.thd+n vs. input amplitude ? 1 khz tone, 44.1 khz:192 khz ................................................. 77 figure 83.thd+n vs. input amplitude ? 1 khz tone, 44.1 khz:48 khz ................................................... 77 figure 84.thd+n vs. input amplitude ? 1 khz tone, 192 khz:48 khz .................................................... 77 figure 85.thd+n vs. input frequency ? 0 dbfs, 48 khz:44.1 khz ......................................................... 78 figure 86.thd+n vs. input frequency ? 0 dbfs, 48 khz:96 khz ............................................................ 78 figure 87.thd+n vs. input frequency ? 0 dbfs, 44.1 khz:48 khz ......................................................... 78 figure 88.thd+n vs. input frequency ? 0 dbfs, 96 khz:48 khz ............................................................ 78 figure 89.total power supply current vs. differential mode receiver input sample frequency ............. 78
8 ds692pp2 CS8422 list of tables table 1. vlrck behavior ....................................................................................................... .................. 35 table 2. pll clock ratios ..................................................................................................... .................... 38 table 3. hardware mode control settings ....................................................................................... ......... 40 table 4. hardware mode serial audio format control ............................................................................ .41 table 5. hardware mode serial audio port clock control ........................................................................ 41 table 6. summary of software register bits .................................................................................... ........ 44 table 7. gpo pin configurations ............................................................................................... ............... 50 table 8. isclk/ilrck ratios and sisf settings .. ............................................................................... .... 53 table 9. osclk1/olrck1 ratios and sosf1 settings .......................................................................... 54 table 10. osclk2/olrck2 ratios and sosf1 settings ........................................................................ 55
ds692pp2 9 CS8422 1. pin description 1.1 software mode pin name pin # pin description rx[3:0], rxp/rxn[1:0] 1 2 5 6 aes3/spdif input (input) - single-ended or differential receiver inputs carrying aes3 or s/pdif encoded digital data. rx[3:0] comprise the single- ended input multiplexer. rxp[1:0] comprise the non-inverting inputs of the differential input multip lexer and rxn[1:0] comprise the inverting inputs of the differential input multiplexer. unused inputs should be tied to agnd/dgnd. va 3 analog power (input) - analog power supply, nominally +3.3 v. care should be taken to ensure that this supply is as noise-free as possible, as noise on this pin will directly affect the jitter perfor- mance of the recovered clock. agnd 4 analog ground (input) - ground for the analog circuitry in the chip. agnd and dgnd should be connected to a common ground area under the chip. ad0/cs 7 address bit 0 (i2c) / soft ware chip select (spi) (input) - a falling edge on this pin puts the CS8422 into spi control port mode. with no falling edge, the CS8422 defaults to i2c mode. in i2c mode, ad0 is a chip address pin. in spi mode, cs is used to enable the control port interface on the CS8422. see ?control port description? on page 42 . ad1/cdin 8 address bit 1 (i2c) / serial control data in (spi) (input) - in i2c mode, ad1 is a chip address pin. in spi mode, cdin is the input data li ne to the control port interface. see ?control port description? on page 42 . scl/cclk 9 software clock (input) - serial control interface clock used to clock control data bits into and out of the CS8422. sda/cdout 10 serial control data i/o (i2c) / data out (spi) (input/output) - in i2c mode, sda is the control i/o data line. in spi mode, cdout is the output dat a from the control port interface on the CS8422. 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 top-down view 32-pin qfn package thermal pad xto ilrck gpo3 olrck1 osclk1 sdout1 osclk2 va agnd ad0/cs rx0/rxp0 sdout2 vl tdm_in olrck2 rx1/rxn0 rx2/rxp1 rx3/rxn1 rmck gpo2 vd_filt v_reg xti ad1/cdin sda/cdout scl/cclk isclk gpo1 gpo0 sdin dgnd rst
10 ds692pp2 CS8422 xti 11 crystal/oscillator in (input) - crystal or digital clock in put for master clock. see ?src master clock? on page 38 for more details. xto 12 crystal out (output) - crystal output for master clock. see ?src master clock? on page 38 for more details. ilrck 13 serial audio input left/right clock ( input / output ) - word rate clock for the audio data on the sdin pin. isclk 14 serial audio input bit clock ( input / output ) - serial bit clock for audio data on the sdin pin. sdin 15 serial audio input data port ( input ) - audio data serial input pin. gpo[3:0] 16 17 18 30 general purpose outputs (output) - see page 50 for details. in i2c mode, a 20 k pull-up resistor to vl on gpo2 will set ad2 chip address bit to 1, otherwise ad2 will be 0. v_reg 19 voltage regulator in ( input ) - regulator power supply input, nominally +3.3 v. vd_filt 20 digital voltage regulator (output) - digital core voltage regulator output. should be connected to digital ground through a 10 f capacitor. typically +2.5 v. cannot be used as an external voltage source. dgnd 21 digital & i/o ground (input) - ground for the i/o and core logic. agnd and dgnd should be con- nected to a common ground area under the chip. vl 22 logic power ( input ) - input/output power supply, typica lly +1.8 v, +2.5 v, +3.3 v, or +5.0 v. sdout2 23 serial audio output 2 data port (output) - audio data serial output 2 pin. osclk2 24 serial audio output 2 bit clock (input/output) - serial bit clock for audio data on the sdout2 pin. olrck2 25 serial audio output 2 left/right clock ( input / output ) - word rate clock for the audio data on the sdout2 pin. tdm_in 26 serial audio output 1 tdm input ( input ) - time division multiplexing serial audio data input. should remain grounded when not used. see ?time division multiple xing (tdm) mode? on page 27 . sdout1 27 serial audio output 1 data port ( output ) - audio data serial output 1 pin. osclk1 28 serial audio output 1 bit clock ( input / output ) - serial bit clock for audio data on the sdout 1 pin. olrck1 29 serial audio output 1 left/right clock ( input / output ) - word rate clock for the audio data on the sdout 1 pin. rmck 31 recovered master clock (output) - recovered master clock from the pll. frequency is 128x, 192x, 256x, 384x, 512x, 768x, or 1024x fs, where fs is the samp le rate of the incoming aes3- compatible data, or isclk/64. rst 32 reset (input) - when rst is low the CS8422 enters a low powe r mode and all internal states are reset. on initial power up rst must be held low until the power supply is stable and all input clocks are stable in frequency and phase. thermal pad - thermal pad - thermal relief pad. should be connecte d to the ground plane for optimized heat dis- sipation. pin name pin # pin description
ds692pp2 11 CS8422 1.2 hardware mode pin name pin # pin description rxp/rxn[1:0] 1 2 5 6 aes3/spdif input (input) - differential receiver inputs carrying aes3 or s/pdif encoded digital data. rxp[1:0] comprise the non-inverting inputs of the differential input multiplexer; and rxn[1:0] comprise the inverting inputs of the input multiplexer. unused inputs should be tied to agnd. va 3 analog power (input) - analog power supply, nominally +3.3 v. care should be taken to ensure that this supply is as noise-free as possible, as noise on this pin will directly affect the jitter performance of the recovered clock. agnd 4 analog ground (input) - ground for the analog circuitry in the chip. agnd and dgnd should be connected to a common ground area under the chip. saof 7 serial audio output format select (input) - used to select the serial audio output format after reset. see table 4 on page 41 for format settings. ms_sel 8 master/slave select (input) - used to select master or slave settings for the input and output serial audio ports after reset. see table 5 on page 41 for format settings. nv/rerr 9 non-validity receiver error/receiver error (output) - receiver error indicator. nverr is output by default, rerr is selected by a 20 k resistor to vl. v/audio 10 validity data/audio ( output ) - if a 20 k pull-down is present on this pin, it will output serial validity data from the aes3 receiver, clocked by the rising and falling edges of olrck2 in master mode. if a 20 k pull-up is present, the pin will be low when vali d linear pcm data is present at the aes3 input. xti 11 crystal/oscillator in (input) - crystal or digital clock input for master clock. see ?src master clock? on page 38 . xto 12 crystal out (output) - crystal output for master clock. see ?src master clock? on page 38 . 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 top-down view 32-pin qfn package thermal pad xto mclk_out src_unlock sdout1 osclk2 va agnd saof rxp0 sdout2 vl tdm_in olrck2 rxn0 rxp1 rxn1 rmck tx/u vd_filt v_reg xti ms_sel v/audio nv/rerr tx_sel c rcbl rx_sel dgnd rst osclk1 olrck1
12 ds692pp2 CS8422 mclk_out 13 buffered mclk (output) - buffered output of xti clock. if a 20 k pull-up resistor to vl is present on this pin, the src mclk source will be the pll clock, otherwise it will be the ring oscillator. tx_sel 14 tx pin mux selection (input) - used to select the aes3-compatib le receiver input for pass-through to the tx pin. rx_sel 15 receiver mux selection (input) - used to select the active aes3-compatible receiver input. rcbl 16 receiver channel status block ( output ) - indicates the beginning of a received channel status block. will go high for one subframe during each z preamble following the fi rst detected z preamble. if no z preamble is detected, output is indeterminate. see figure 19 on page 36 for more detail. c17 channel status data ( output ) - serial channel status data output from the aes3-compatible receiver, clocked by the rising and falli ng edges of olrck2 in master mode. a 20 k pull-up resistor to vl must be present on this pin to put the part in hardware mode. tx/u 18 receiver mux pass-through/user data ( output ) - if no 20 k pull-up resistor is present on this pin it will output a copy of the receiver mux i nput selected by the tx _sel pin. if a 20 k pull-up resistor to vl is present on this pin, it will output serial user data from the aes3 receiver, clocked by the rising and falling edges of olrck2 in master mode. v_reg 19 voltage regulator in ( input ) - regulator power supply input, nominally +3.3 v. vd_filt 20 digital voltage regulator out (output) - digital core voltage regulator output. should be connected to digital ground through a 10 f capacitor. cannot be used as an external voltage source. dgnd 21 digital & i/o ground (input) - ground for the i/o and core logic. agnd and dgnd should be con- nected to a common ground area under the chip. vl 22 logic power ( input ) - input/output power supply, typica lly +1.8 v, +2.5 v, +3.3 v, or +5.0 v. sdout2 23 serial audio output 2 data port (output) - audio data serial output 2 pin. osclk2 24 serial audio output 2 bit clock (input/output) - serial bit clock for audio data on the sdout2 pin. olrck2 25 serial audio output 2 left/right clock (input/output) - word rate clock for the audio data on the sdout2 pin. tdm_in 26 serial audio output 1 tdm input (input) - time division multiplexing serial audio data input. grounded when not used. see ?time division multiplexing (tdm) mode? on page 27 for details. sdout1 27 serial audio output 1 data port (output) - audio data serial output 1 pin. a 20 k pull-up to vl present on this pin will disable de-emphasis auto detect. osclk1 28 serial audio output 1 bit clock (input/output) - serial bit clock for audio data on the sdout1 pin. olrck1 29 serial audio output 1 left/right clock (input/output) - word rate clock for the audio data on the sdout1 pin. src_unlock 30 src unlock indicator ( output ) - indicates when the src is unlocked. see ?src locking? on page 37 for more details. rmck 31 recovered master clock (output) - recovered master clock from the pll. frequency is 128 x, 256 x, or 512 x fs, where fs is the sample rate of the incoming aes3-compa tible data or isclk/64. if a 20 k pull-up to vl is present on this pin, the sdout2 mclk source will be rmck, otherwise it will be the clock input through xti-xto. rst 32 reset (input) - when rst is low the CS8422 enters a low power mode and all internal states are reset. on initial power up rst must be held low until the power supply is stable and all input clocks are stable in frequency and phase. thermal pad - thermal pad - thermal relief pad. should be connected to the ground plane for optimized heat dissi- pation. pin name pin # pin description
ds692pp2 13 CS8422 2. characteristics and specifications (all min/max characteristics and specific ations are guaranteed over the specif ied operating conditions. typical per- formance characteristics and specifications are derived fr om measurements taken at nominal supply voltages and t a = 25 c.) recommended operating conditions gnd = 0 v, all voltages with respect to 0 v. absolute maximum ratings dgnd = agnd = 0 v; all voltages with respect to 0 v. op eration beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. transient currents of up to 100 ma will not cause scr latch-up. parameter symbol min nominal max units power supply voltage vl va v_reg 1.71 3.135 3.135 3.3 3.30 3.30 5.25 3.465 3.465 v v v ambient operating temperature: commercial grade automotive grade t a -40 -40 - - +85 +105 c c parameter symbol min max units power supply voltage vl va v_reg -0.3 -0.3 -0.3 6.0 4.3 4.3 v v v input current, any pin except supplies (note 1) i in -10ma input voltage, any pin except rxp[1:0], rxn[1:0], or rx[3:0] v in -0.3 vl+0.4 v input voltage, rxp[1:0], rxn[1:0], or rx[3:0] v in -0.3 va+0.4 v ambient operating temperature (power applied) t a -55 +125 c storage temperature t stg -65 +150 c
14 ds692pp2 CS8422 performance specifications - sample rate converter xti-xto = 24.576 mhz; input signal = 1.000 khz, measurement bandwidth = 20 to fso/2 hz, and word width = 24-bits. (note 2) notes: 2. fsi indicates the input sample rate . fso indicates the output sample rate. numbers separated by a colon indicate the ratio of fsi to fso. digital filter characteristics parameter min typ max units resolution 16 - 24 bits sample rate slave master xti/2048 xti/512 - - xti/128 xti/128 khz khz sample rate ratio - upsampling - - 1:6 fsi:fso sample rate ratio - do wnsampling - - 6:1 fsi:fso interchannel gain mismatch - 0.0 - db interchannel phase deviation - 0.0 - degrees gain error -0.2 - 0 db peak idle channel noise component - - -144 dbfs dynamic range - unweighted (20 hz to fso/2, -60 dbfs input) 32 khz:48 khz - 140 - db 44.1 khz:48 khz - 141 - db 44.1 khz:192 khz - 138 - db 48 khz:44.1 khz - 140 - db 48 khz:96 khz - 141 - db 96 khz:48 khz - 140 - db 192khz:32khz - 141 - db total harmonic distortion + noise (20 hz to fso/2, 0 dbfs input) 32 khz:48 khz - -134 - db 44.1 khz:48 khz - -134 - db 44.1 khz:192 khz - -133 - db 48 khz:44.1 khz - -131 - db 48 khz:96 khz - -135 - db 96 khz:48 khz - -136 - db 192khz:32khz - -137 - db parameter min typ max units passband (upsamplin g or downsampling) -- 0.4535* min(fsi,fso) fs passband ripple - - 0.05 db stopband (downsampling) 0.5465*fso --fs stopband attenuation 125 - - db group delay see ?group delay? on page 69
ds692pp2 15 CS8422 dc electrical characteristics agnd = dgnd = 0 v; all voltages with respect to 0 v. notes: 3. power-down mode is defined as rst = low with all clocks and data lines held static and no crystal attached across xti - xto. 4. normal operation is defined as rst = high. the typical values shown were measured with the digital interface receiver in differential mode, serial au dio output port 1 in master mode sourced by the src, and serial audio output port 2 in master mode sourced by the aes3 receiver output. parameter min typ max units power-down mode (note 3) supply current in power down va v_reg vl = 1.8 v vl = 2.5 v vl = 3.3 v vl = 5.0 v - - - - - - 4.7 1 0.3 7.1 16.9 102.6 - - - - - - a a a a a a normal operation (note 4) supply current at 48 khz fsi and fso va v_reg vl = 1.8 v vl = 2.5 v vl = 3.3 v vl = 5.0 v - - - - - - 7.6 9.4 2.7 3.8 5.2 24 - - - - - - ma ma ma ma ma ma supply current at 192 khz fsi and fso va v_reg vl = 1.8 v vl = 2.5 v vl = 3.3 v vl = 5.0 v - - - - - - 32.4 18.9 6.2 8.8 12 50.4 - - - - - - ma ma ma ma ma ma
16 ds692pp2 CS8422 digital interface specifications agnd = dgnd = 0 v; all voltages with respect to 0 v. notes: 5. when a digital signal is sent to the aes rx pins, th e pins will draw approximatel y 730 a from the digital signal?s supply from the time reset is de-assert ed until the rx_mode, rx_ sel, and input_type bits in register 03h are properly configured to allow a digital input signal on the driven pins, see section 11.3 on page 48 . 6. maximum sensitivity in accord ance with aes3-2003 section 8.3.3. measured with eye diagram height at the specified voltage and width of at leas t 50% of one-half the biphase symbol period. parameter symbol min typ max units input leakage current (note 5) i in --+32 a input capacitance i in -8-pf digital interface receiver - rxp[1:0], rxn[1:0], rx[3:0] differential input sensitivity, rxp to rxn (note 6) --200mvpp differential input impedance, rxp and rxn to gnd - 11 - k single-ended input sensitivity, rx pins, receiver input mode 1 (note 6) --200mvpp single-ended input impedance, rx pins, receiver input mode 1 - 11 - k high-level input voltage, rx pins in digital mode v ih 0.55xva - va+0.3 v low-level input voltage, rx pins in digital mode v il -0.3 - 0.8 v digital i/o high-level output voltage (i oh = -4 ma) v oh .77xvl - -v low-level output voltage (i ol = 4 ma) v ol - - 0.6 v high-level input voltage v ih 0.65xvl - -v low-level input voltage v il - - 0.3xvl v input hysteresis - 0.2 - v
ds692pp2 17 CS8422 switching specifications inputs: logic 0 = 0 v, logic 1 = vl; c l = 20 pf. parameter symbol min typ max units rst pin low pulse width (note 7) 1- -ms pll clock recovery sample rate range (note 8) 28 - 216 khz rmck output jitter (note 9) differential rx mode single-ended rx mode - - 200 475 - - ps rms ps rms rmck output duty cycle 45 50 55 % xti frequency crystal 12 - 27.000 mhz digital clock source 1.024 - 49.152 mhz xti pulse width high/low 9- -ns mclk_out duty cycle 45 - 55 % vl = 3.3v, 5v rmck output frequency - - 49.152 mhz mclk_out frequency - - 49.152 mhz slave mode isclk frequency - - 49.152 mhz isclk high time t sckh 9.2 - - ns isclk low time t sckl 9.2 - - ns osclk frequency --26.9mhz osclk high time t sckh 16.7 - - ns osclk low time t sckl 16.7 - - ns i/olrck edge to i/osclk rising edge t lcks 5.7 - - ns i/osclk rising edge to i/olrck edge t lckd 4.2 - - ns osclk falling edge/olrck edge to sdout output valid t dpd --13.7ns sdin/tdm_in setup time before i/osclk rising edge t ds 2.2 - - ns sdin/tdm_in hold time after i/osclk rising edge t dh 5.5 - - ns tdm mode olrck high time (note 10) t lrckh 20 - - ns tdm mode olrck rising edge to osclk rising edge t fss 5.3 - - ns tdm mode osclk rising edge to olrck falling edge t fsh 4.2 - - ns master mode i/osclk frequency (non-tdm mode) 48*fsi/o - 128*fsi/o mhz i/olrck duty cycle 49.5 - 50.5 % i/osclk duty cycle 45 - 55 % i/osclk falling edge to i/olrck edge t lcks --4.2ns osclk falling edge to sdout output valid t dpd --4.6ns
18 ds692pp2 CS8422 notes: 7. after powering up the CS8422, rst should be held low until the power supplies and clocks are settled. 8. if isclk is selected as the clock source fo r the pll, then the sample rate = isclk/64. sdin/tdm_in setup time be fore i/osclk rising edge t ds 2.2 - - ns sdin/tdm_in hold time after i/osclk rising edge t dh 5.5 - - ns tdm mode osclk frequency (note 11) - - 49.152 mhz tdm mode osclk falling edge to olrck edge t fsm --4.2ns vl = 1.8 v, 2.5 v rmck output frequency --31mhz mclk_out frequency --31mhz slave mode isclk frequency - - 49.152 mhz isclk high time t sckh 9.2 - - ns isclk low time t sckl 9.2 - - ns osclk frequency --15.7mhz osclk high time t sckh 28.7 - - ns osclk low time t sckl 28.7 - - ns i/olrck edge to i/osclk rising edge t lcks 7.4 - - ns i/osclk rising edge to i/olrck edge t lckd 6.2 - - ns osclk falling edge/olrck edge to sdout output valid t dpd --25.6ns sdin/tdm_in setup time be fore i/osclk rising edge t ds 4.7 - - ns sdin/tdm_in hold time after i/osclk rising edge t dh 7.3 - - ns tdm mode olrck high time (note 10) t lrckh 20 - - ns tdm mode olrck rising edge to osclk rising edge t fss 7.0 - - ns tdm mode osclk rising edge to olrck falling edge t fsh 6.2 - - ns master mode i/osclk frequency (non-tdm mode) 48*fsi/o - 128*fsi/o mhz i/olrck duty cycle 45 - 55 % i/osclk duty cycle 45 - 55 % i/osclk falling edge to i/olrck edge t lcks --5.7ns osclk falling edge to sdout output valid t dpd --5.4ns sdin/tdm_in setup time be fore i/osclk rising edge t ds 4.7 - - ns sdin/tdm_in hold time after i/osclk rising edge t dh 7.3 - - ns tdm mode osclk frequency (note 11) --31mhz tdm mode osclk falling edge to olrck edge t fsm --5.7ns parameter symbol min typ max units
ds692pp2 19 CS8422 9. typical base band jitter in acco rdance with aes-12id- 2006 section 3.4.2. meas urements are time in- terval error (tie) taken with 3rd order 100 hz to 40 khz band-pass filter. measured with sample rate = 48 khz. 10. olrck must remain high for at least 1 osclk pe riod and at most 255 osclk periods in tdm mode. 11. in tdm formatted master mode, the os clk frequency is fixed at 256*olrck. t ds olrck (input) t dh t sckh t sckl t fsh t fss osclk (input) tdm_in (input) sdout (output) msb t dpd msb-1 msb msb-1 t lrckh t ds msb t dh t dpd msb-1 i/olrck (input) i/osclk (input) sdin (input) sdout (output) msb msb-1 t sckh t sckl t lcks t lckd figure 1. non-tdm slave mode timi ng figure 2. tdm slave mode timing t ds olrck (output) t dh t dpd t fsm osclk (output) tdm_in (input) sdout (output) msb msb-1 msb msb-1 t ds msb t dh t dpd msb-1 t lcks i/olrck (output) i/osclk (output) sdin (input) sdout (output) msb msb-1 figure 3. non-tdm master mode timi ng figure 4. tdm master mode timing
20 ds692pp2 CS8422 switching characteristics - control port - spi mode inputs: logic 0 = 0 v, logic 1 = vl; c l = 20 pf. notes: 12. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 13. data must be held for sufficient time to bridge the transition time of cclk. 14. cdout should not be sampled during this time. 15. for f sck < 1 mhz. parameter symbol min max unit cclk clock frequency f sck 06.0mhz rst rising edge to cs falling t srs 500 - s cclk edge to cs falling (note 12) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 13) t dh 15 - ns cclk falling to cdout valid (note 14) t scdov -100ns time from cs rising to cdout high-z t cscdo -100ns cdout rise time t r1 -25ns cdout fall time t f1 -25ns cclk and cdin rise time (note 15) t r2 -100ns cclk and cdin fall time (note 15) t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst cdout t scdov t scdov t cscdo hi-impedance figure 5. spi mode timing
ds692pp2 21 CS8422 switching characteristics - control port - i2c mode inputs: logic 0 = 0 v, logic 1 = vl; c l = 20 pf. notes: 16. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - s bus free time between transmissions t buf 4.7 - s start condition hold time (p rior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 16) t hdd 10 - ns sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rd - 1000 ns fall time scl and sda t fc , t fd -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t lo w t hdd t high t sud stop s tart sda scl t irs rst t hdst t rc t fc t sust t susp start stop repeated t rd t fd t ack figure 6. i2c mode timing
22 ds692pp2 CS8422 3. typical connection diagrams 3.1 software mode CS8422 vd_filt serial audio input device crystal/clock source microcontroller serial audio input device serial audio output device aes3/spdif/iec60958 receiver circuitry clock routing, interrupt control, channel-status, and user data output tdm output device rx0/rxp0 1 rx1/rxn0 2 rx2/rxp1 5 rx3/rxn1 5 ilrck 13 isclk 14 sdin 15 xti 11 xto 12 ad0/cs 7 ad1/cdin 8 scl/cclk 9 sda/cdout 10 rst 32 gpo0 16 gpo1 17 gpo2 18 gpo3 30 d g n d 21 a gnd 4 20 10 f 0.1 f + rmck 31 sdout2 23 osclk2 24 olrck2 25 tdm_in 26 sdout1 27 olrck1 29 osclk1 28 10 f 0.1 f + v a 3 +3.3v v l +1.8v to +5v 0.1 f 22 10 f 0.1 f + v_r eg 19 +3.3v 20 k +vl figure 7. typical connection diagram, software mode see section 12.3 for details.
ds692pp2 23 CS8422 3.2 hardware mode CS8422 vd_filt serial audio input device aes3/spdif/iec60958 receiver circuitry tdm output device rxp0 1 rxn0 2 rxp1 5 rxn1 6 a g n d 4 d gn d 21 sdout2 23 osclk2 24 olrck2 25 13 mclk_out tdm_in 26 sdout1 29 osclk1 28 olrck1 27 serial audio input device crystal/clock source xti 11 xto 12 10 f 0.1 f + 20 hardware control circuitry rx_sel 15 tx_sel 14 src_unlock 30 nv/rerr 9 rcbl 16 c 17 tx/u 18 v/audio 10 +vl 20 k rst 32 saof 7 ms_sel 8 channel status, user, and validity data handling and tx passthrough + 10 f 0.1 f v a +3.3v 3 + 10 f 0.1 f v_r e g +3.3v 19 0.1 f v l +1.8v to +5v 22 31 rmck 20 k +vl 20 k +vl 20 k +vl 20 k . see section 12.3 for details.
24 ds692pp2 CS8422 4. overview the CS8422 is a 24-bit, high performance, monolithic cmos stereo asynchronous sample rate converter with inte- grated digital audio interface receiv er that decodes audio data according to eiaj cp1201, iec-60958, aes3, and s/pdif interface standards. audio data is input through either a 3- wire serial audio port or the aes3-compa tible digital interface receiver. audio data is output through one of two 3-wire serial audio output ports. the serial au dio ports are capable of 24-, 20-, 18- , or 16-bit word lengths. data in to the digital interface receiver can be up to 24-bit. input and output data can be completely asynchronous, synchronous to an external dat a clock through xti, or synchronous to the master clock recovered from the incomi ng s/pdif or aes3 data. CS8422 can be controlled either in software mode or in a stand-alone hardware mode. in software mode, the user can control the device through either a spi or i2c control port. target applications include digital recording systems (d vd-r/rw, cd-r/rw, pvr, dat, md, and vtr), digital mix- ing consoles, high quality d/a, effe cts processors, computer audio system s, and automotive audio systems. figure 7 and figure 8 show typical connections to the CS8422. 5. three-wire serial in put/output audio port the CS8422 provides two independent 3- wire serial audio output ports, and a 3-wire serial audio input (only avail- able in software mode). the interface format should be chos en to suit the attached device either through the control port in software mode, or through the ms_sel and saof pins in hardware mode. the following parameters are adjustable: hardware mode ? master or slave mode operation ? master-mode mclk-to-olrck (olrck1 and olrck2) ratios: 128, 256, and 512 ? audio data resolution of 16, 20, or 24 bits ? left-justified, i2s, or righ t-justified serial data formats ? multi-channel tdm serial audio format (serial audio output 1 only) software mode ? master or slave mode operation ? master-mode mclk-to-ilrck and mclk-to-olrck (olrck1 and olrck2) ratios: 64, 128, 192, 256, 384, 512, 768, and 1024 ? audio data resolution of 16, 18, 20, or 24 bits ? left-justified, i2s, or righ t-justified serial data formats ? multi-channel tdm serial audio format ? aes3 direct output format figures 9 , 10 , 11 , and 12 show the standard input/output formats ava ilable. the tdm serial audio format is de- scribed in section 5.1.5 on page 27 . for more information about serial audio formats, refer to the cirrus logic ap- plications note an282, ?the 2-channel serial audio interface: a tutorial?, available at www.cirrus.com .
ds692pp2 25 CS8422 5.1 serial port clock operation 5.1.1 master mode when a serial port is set to master mode, its left/ri ght clock (ilrck, olrck1, or olrck2), and its serial bit-clock (isclk, osclk1, or osclk2) are outputs. if a serial output is sourced directly by the aes3 re- ceiver, then that serial port?s left /right clock and serial bit-clock will be synchronous with rmck. if a serial port is routed to or from the sample rate converter (s rc), then that serial port?s left/right clock and serial bit-clock can be synchronous with either the xt i-xto or rmck when it is in master mode. if a serial output is source directly by the serial input port without the use of the src, then all associated clocks must be synchronous, so both serial ports must use the same master clock source. it is for this reason that, when in this mode, the serial output clock control is done through the serial audio input clock control (07h) register. 5.1.2 slave mode when a serial port is in slave mode, its left/right clock (ilrck, olrck1, or olrck2), and its serial bit- clock (isclk, osclk1, or osclk2) are inputs. if the serial input or a serial output has the src in its data path, then the serial port?s lrck and sclk may be asynchronous to all other serial ports. the left/right clock should be continuous, but the duty cycl e can be less than 50% if enough serial clocks are present in each associated lrck phase to clock all of the data bits. if there are fewer sclk periods than required to clock all the bits present in one half lrck period in left- justified and i2s modes, data will be truncated beginning with the lsb. in right-justified modes, the data will be invalid. if a serial audio output is operated in slave mo de and source d directly by the aes3 receiver or the serial input port without the use of the sample rate converte r, then the olrck supplied to the serial audio output should be synchronous to fsi or ilrck to avoid skipped or repeated samples. the oslip bit ( ?interrupt status (14h)? on page 59 ) is provided to indicate when skipped or repeated samples occur. if the input sample rate, fsi or ilrck, is greater than the slave-mode olrck frequency, then dropped samples will occur. if fsi or ilrck is less than the slave-mode olrck fre quency, then samples will be repeated. in either case the osli p bit will be set to 1 and will not be clea red until read th rough the control port. 5.1.3 hardware mode control in hardware mode, the serial audio input port is not av ailable. sdout1 is the serial data output from the sample rate conver ter, and sdout2 is the serial audio output dire ctly from the aes3-c ompatible receiver. because there is no serial audio input available in hardware mode, all audio data input is done through the aes3-compatible receiver . in hardware mode, the serial output ports are controlled through the saof and ms_sel pins. see ?hardware mode serial audio port control? on page 40 for more details. in hardware mode, there are always 64 sclk periods per lrck period when a serial port is set to master mode. 5.1.4 software mode control in software mode, the CS8422 provides a serial audio input port and two serial audio output ports. each serial port?s clocking and data routing options are fully configurable as shown in serial audio input data format (0bh) , serial audio output data format - sdout1 (0ch) , and serial audio output data format - sdout2 (0dh) registers, found on pages 53 , 54 , and 55 .
26 ds692pp2 CS8422 i/olrck i/osclk msb lsb msb lsb channel a sdin sdout msb channel b figure 9. serial audio interface format ? i2s msb lsb msb lsb msb i/olrck i/osclk sdin sdout channel a channel b figure 10. serial audio interface format ? left-justified i/olrck i/osclk channel a sdin channel b msb sdout msb msb msb lsb lsb lsb lsb msb extended msb extended figure 11. serial audio interface format ? right-justified (master mode only) olrck osclk sdout channel a channel b lsb msb v u c z lsb msb v u c z figure 12. serial audio interface format ? aes3 direct output
ds692pp2 27 CS8422 5.1.5 time division multiplexing (tdm) mode tdm mode allows several tdm-compat ible devices to be serially connected together allowing their cor- responding serial output data to be multiplexed onto one line for input into a dsp or other tdm capable input device. in tdm mode, the tdm_in pin is used to input tdm- formatted data while the sdout1 or sdout2 (soft- ware mode only) pin is used to output tdm data. if the CS8422 is the first tdm device in the chain, it should have its tdm_in connected to gnd. data is transmitted from sdoutx (sdout1 or sdout2) most significant bit first on the first falling osclkx edge after an olrckx rising edge and is valid on the rising edge of osclkx. 5.1.5.1 tdm master mode in tdm master mode, osclkx frequency is fixe d at 256*olrckx (where x = 1 or x = 2 depending on which serial output port is selected as being in tdm m ode). each sample time slot is 32 bit-clock periods long; providing 8 channels of digital audio multiplexe d together, with the first two channels being supplied by the CS8422 which has been placed in master mode. an osclkx-wide olrckx pulse identifies the start of a new frame, with the valid data sample begi nning one osclkx after the olrckx rising edge. in tdm master mode, the master clock source for the td m serial port must be 256, 512, or 1024*fso. valid data lengths are 16, 18, 20, or 24 bits. figure 13 shows the interface format for tdm master mode. 5.1.5.2 tdm slave mode in tdm slave mode, the number of channels that can by multiplexed to one serial data line depends on the output sample rate. for slave mode, osclkx mu st operate at n*64*fso, where n is the number of CS8422?s in the tdm chain. for example, if fso = 96 khz, n = 4 (8 channels of serial audio data), osclkx frequency must be 24.576 mhz. note that the maximum osclkx frequency in slave mode is a function of the vl supply voltage, as shown in ?switching specifications? on page 17 . figure 14 shows the interface format for tdm slave mode. 5.1.5.3 hardware mode control in hardware mode, tdm mode is selected through the saof pin. see section 8.1 on page 40 for more details. 5.1.5.4 software mode control in software mode, tdm mode is selected through the serial audio output data format - sdout1 (0ch) register, found on page 54 .
28 ds692pp2 CS8422 olrck osclk sdout/ tdm_in msb 32 osclks sdout 4, ch a 32 osclks sdout 4, ch b 32 osclks sdout 3, ch a 32 osclks sdout 3, ch b 32 osclks sdout 2, ch a 32 osclks sdout 2, ch b 32 osclks sdout 1, ch a 32 osclks sdout 1, ch b msb msb msb msb msb msb msb msb lsb data figure 13. tdm master mode timing diagram olrck osclk sdout/ tdm_in msb 32 osclks sdout 4, ch a 32 osclks sdout 4, ch b 32 osclks sdout 3, ch a 32 osclks sdout 3, ch b 32 osclks sdout 2, ch a 32 osclks sdout 2, ch b 32 osclks sdout 1, ch a 32 osclks sdout 1, ch b msb msb msb msb msb msb msb msb lsb data figure 14. tdm slave mode timing diagram ilrck isclk sdin olrck osclk sdout tdm_in olrck osclk sdout tdm_in ilrck isclk sdin olrck osclk sdout pcm source 2 olrck osclk sdout pcm source 1 CS8422 1 slave CS8422 2 slave lrck sclk sdin dsp master olrck osclk sdout tdm_in ilrck isclk sdin CS8422 3 slave olrck osclk sdout tdm_in ilrck isclk sdin CS8422 4 slave olrck osclk sdout pcm source 3 olrck osclk sdout pcm source 4 figure 15. tdm mode configurat ion (all CS8422 outputs are slave) ilrck isclk sdin olrck osclk sdout tdm_in CS8422 1 olrck osclk sdout pcm source 2 olrck osclk sdout pcm source 1 master lrck sclk sdin dsp slave olrck osclk sdout tdm_in ilrck isclk sdin CS8422 4 slave olrck osclk sdout tdm_in ilrck isclk sdin CS8422 2 slave olrck osclk sdout tdm_in ilrck isclk sdin CS8422 3 slave olrck osclk sdout pcm source 3 olrck osclk sdout pcm source 4 figure 16. tdm mode configuration (first CS8422 output is master, all others are slave)
ds692pp2 29 CS8422 6. digital interface receiver the CS8422 includes a digital interface receiver that can receive and decode audio data ac cording to the aes3, iec60958, s/pdif, and eij cp1201 interface standards. the CS8422 uses either a 4:1 single-ended or 2:1 different ial input mux to select the input pin(s) that will receive input data to be decoded. a low-jitter clock (rmck) is re covered using a pll, which provides the digital interface receiver with a master clock. the decoded audio data c an either be routed through the src for sample rate con- version, or can be an output on one of two serial audio output ports. the ch annel status and q-s ubcode data portion of the user data are assembled and buffered in channel status registers (23h - 2ch) and q-channel subcode (19h - 22h) , and may be accessed through the control port in either spi or i2c mode. 6.1 aes3 and s/pdif standards this document assumes that the user is familiar with the aes3 and s/pdif data formats. it is advisable to have current copies of the aes3, iec60958, iec619 37, and eij cp1201 specifications on hand for easy reference. the latest aes3 standard is available from the audio engineering society at www.aes.org . the latest iec60958/61937 standard is available from th e international electrotechnical commission at www.iec.ch . the latest eiaj cp-1201 standard is avail able from the japanese electronics bureau at www.jei- ta.or.jp/eiaj/ . application note 22: overview of digital audio interface data structures , available at www.cirrus.com , con- tains a useful tutorial on digital audio specifications, bu t it should not be considered a substitute for the stan- dards. the paper titled an understanding and implementation of the scms serial copy management system for digital audio transmission , by clifton sanchez, is an excellent tuto rial on scms. it is available from the aes as reprint 3518. 6.2 receiver input multiplexer the CS8422?s receiver input multiple xer allows input of data compatib le with aes3, s/pdif, iec60958, and eiaj cp-1201 standards. for information abou t recommended receiver input circuits, see ?external receiv- er components? on page 64 . 6.2.1 hardware mode control in hardware mode, the receiver input multiplexer is limited to a selectio n between two differential inputs, rxp0/rxn0 and rxp1/rxn1. the receiver input mult iplexer will decode data pres ent at the differential input selected by the rx_sel pin. see section 8. ?hardware mode control? on page 39 for more details. multiplexer inputs are floating when not selected. unused inputs should be tied to agnd/dgnd 6.2.2 software mode control in software mode, CS8422 offers either a 4:1 single-e nded, or a 2:1 differential input multiplexer to ac- commodate switching betw een up to four ch annels of aes3 or s/pdif-com patible data input. in single- ended mode, the CS8422 can switch between four single -ended signals present at rx[3:0]. in differential mode, the CS8422 can switch between two differen tial signals, present on rxp0/rxn0 and rxp1/rxn1. multiplexer inputs are floating when not selected. unused inputs should be tied to agnd/dgnd in software mode, the receiver input multiplexer is controlled through the register described in section 11.3 ?receiver input control (03h)? on page 48 .
30 ds692pp2 CS8422 6.2.2.1 single-ended input mode when the receiver input multiplexer is set to sing le-ended mode, the receiver inputs can be switched be- tween operation as comparator inputs or digital inputs. receiver input mode 1 (analog sensitivity mode) if mode 1 is selected, the inputs are biased at va/ 2 and should be coupled through a capacitor. the rec- ommended value for the ac coupling capacitors is 0.01 f to 0.1 f. the recommended dielectrics for the ac coupling capacitors are c0g or x7r. when the receiver input multiplexer is in mode 1, the receiver input pins allow very low amplitude signals to be decoded reliably. in this mode, the maximum allowable input amplitude is determined by va, which is nominally 3.3 volts. if input amplitudes greater than 3.3 volts to a single pin of the receiver input multi- plexer are required, then attenuation is necessary prio r to the receiver input to avoid damage to the part (see ?attenuating input signals? on page 65 for more details). figure 17 shows the input structure of the receiver in single-ended mode. figure 17. single-ended receiver input structure, receiver mode 1 receiver input mode 2 (d igital sensit ivity mode) if mode 2 is selected, the receiver inputs should be driven by a digital signal referenced to va. in this mode, the selected receiver input is not biased, and does not require the use of an ac coupling capacitor (as with the use of a typical optical receiver output). when the receiver input multiplexer is in mode 2 the specifications for v ih /v il apply (see ?switching spec- ifications? on page 17 for more details). 6.2.2.2 differential input mode when the receiver input multiplexer is set to differential input mode, the inputs are biased at va/2, and require the use of ac coupling capacitors, as mentioned in section 6.2.2.1 . figure 18 shows the structure of the receiver in differential mode. + - va 22 k (22000/n) 22 k agnd rx[3:0] (1500 + 1500/n) (22000/n) note: 1. if rx[3:0] is selected by either the rece iver mux or the tx pass-through mux, n=1. 2. if rx[3:0] is selected by both the receiv er mux and the tx pass-through mux, n=2. 3. if rx[3:0] is not selected at all, n=0 (i.e. high impedance).
ds692pp2 31 CS8422 figure 18. differential receiver input structure 6.3 recovered master clock - rmck the CS8422 has an internal pll which recovers a high-frequency system clock, referred to as the recov- ered master clock (rmck). rmck ca n be generated by in coming aes3-compatible data or the isclk (slave mode and software mo de only). this clock is used as the master clock source for the aes3 receiver and the master-mode serial port that it directly supp lies data to, and is available as an output on the rmck pin. in addition, the user can set the rmck as the mast er clock of either of the two remaining serial ports. 6.3.1 hardware mode control in hardware mode, the rmck fr equency is determined by the incoming aes3 frame rate and the ms_sel pin. rmck can be routed for use as the master clock for the serial audio output associated with sdout1 by connecting a 20 k resistor from the rmck pin to vl. see ?hardware mode control? on page 39 for more details. 6.3.2 software mode control in software mode, the rmck frequency is determined by the incoming aes3 frame rate or isclk/64 (slave mode only). the rmck frequency is configured in the register described in section 11.9 ?recov- ered master clock ratio control & misc. (09h)? on page 52 . if the isclk is chosen as the source for rm- ck, then the ratios in the ?recovered master clock ratio control & misc. (09h)? register reflect the ratio of 64*rmck/isclk. 6.4 xti system clock mode a special clock switching mode is av ailable that allows the clock present at the xti-xto clock input to au- tomatically replace rmck when the pll becomes unlock ed. this is accomplished without spurious transi- tions or glitches on rmck. when clock switching is enabled, th e pll?s loss of lock will cause the xt i-xto clock input to be output on rmck. if a serial port is set master mode and has rm ck as its master clock source, it?s lrck and sclk + - va (22000/n) agnd rxp[1:0] (1500 + 1500/n) (22000/n) rxn[1:0] (1500 + 1500/n) (22000/n) (22000/n) note: 1. if rxp/n[1:0] is selected by either the receiver mux or the tx pass-through mux, n=1. 2. if rxp/n[1:0] is selected by both the re ceiver mux and the tx pass-through mux, n=2. 3. if rxp/n[1:0] is not selected at all, n=0 (i.e. high impedance).
32 ds692pp2 CS8422 frequencies will be derived from the xti-xto clock wh en clock switching has ta ken place and the rmck- to-lrck ratio will be maintained. when clock switching is not enabled and the pll has lost lock, rmck will be derived from the vco idle frequency. the frequency of the rmck output will be still be determined by the rati o selected by the rm- ck[2:0] bits in register 09h, or the ms_sel pin in hardware mode. when the pll has lost lock, the vco idle frequency is equivalent to aes3 input data with fs ? 54 khz 5% (or isclk ? 3.456 mhz 5%). 6.4.1 hardware mode control in hardware mode, xti system clock mode is always enabled. 6.4.2 software mode control in software mode, xti system clock mode is controlled through the register described in section 11.2 ?clock control (02h)? on page 47 . 6.5 aes11 behavior when an aes3-derived olrck is co nfigured as a master, the rising or falling edge of olrck (depending on the serial port in terface format setting) will be within -1.5%(1/fs) to 1.5%(1/fs) from the start of the pre- amble x/z. in master mode, the latency through t he receiver depends on the input sample frequency. in master mode the latency of the audi o data will be 3 frames in aes3 direct mode, and 4 fram es in all other cases. when an aes3-derived olrck is conf igured as a slave, any synchroniz ed input within +/ -25% of an aes3 frame from the positive or negative edge of olrck (d epending on the serial port interface format setting) will be treated as being samp led at the same time. sinc e the CS8422 has no contro l of the olrck in slave mode, the latency of the data through the part will be a multiple of 1/fs plus the intrinsic dela y between ol- rck and the preambles also present in master mode. both of these conditions ar e within the tolerance range se t forth in the aes11 standard. 6.6 error and status reporting while decoding the incoming bi-phase encoded data stream, th e CS8422 has the ability to identify various error conditions. refer to sections 6.6.1 and 6.6.2 for details. 6.6.1 software mode software mode allows the most flex ibility in reading errors. when unma sked, bits in the receiver error register (0ch) indicate the following errors: 1. qcrc ? crc error in q subcode data. 2. ccrc ? crc error in channel status data. 3. unlock ? pll is not locked to incoming bi-phase data stream, or 2 valid z preambles have not yet been detected. 4. v ? data validity bit is set. 5. conf ? the input data stream may be near error condition due to jitter degradation. 6. bip ? bi-phase encoding error. 7. par ? parity error in incoming data.
ds692pp2 33 CS8422 the error bits are ?sticky?, meaning that they are set on the first occurrence of the associated error and will remain set until the user reads the register through the control port. this enables the register to log all unmasked errors that occurred since the last time the register was read. as a result of the bits ?stickiness?, it is necessary to perform two reads on these r egisters to see if the error condition still exists. the receiver error mask register (0eh) allows masking of individual errors. the bits in this register default to 00h and serve as masks for the corr esponding bits of the re ceiver error register. if a mask bit is set to 1, the error is unmasked, which imp lies the following: its occu rrence will be reported in the receiver error register, induce a pulse on rerr, invoke the occurrence of a rerr interrupt, and affect the current audio sample according to the status of the hold bits. the exceptions ar e the qcrc and ccrc errors, which do not affect the current audio sample, even if unmasked. the hold bits allow a choice of: ? holding the previous sample ? replacing the current sample with zero (mute) ? not changing the current audio sample for more details, refer to ?receiver error unmasking (0eh)? on page 56 , ?interrupt unmasking (0fh)? on page 56 , ?interrupt mode (10h)? on page 57 , ?receiver error (13h)? on page 58 , and ?interrupt status (14h)? on page 59 . 6.6.2 hardware mode control in hardware mode, the user may choose to output ei ther the non-valid ity receiver error (nverr) or the receiver error (rerr) on the nv/rerr pin. by defau lt the pin will output the nre rr signal. if upon star- tup a 20 k resistor is connected betwe en the pin and vl, the nv/rerr pin will output the rerr error signal. both rerr and nverr are updated on aes3 subframe boundaries. see ?hardware mode con- trol? on page 39 for more details. nverr ? the previous audio sample is held and passed to the serial audio output port if a parity, bi- phase, confidence or pll lock error occurs during the current sample. rerr ? the previous audio sample is held and passed to the serial audio output port if the validity bit is high, or a parity, bi-phase, confidence or pll lock error occurs during the current sample. 6.7 non-audio detection an aes3 data stream may be used to convey non-audio data, thus it is important to know whether the in- coming aes3 data st ream is digital audio or not. th is information is ty pically conveyed in channel status bit 1, which is extracted automatically by the CS8422. however, certain non-audio sources, such as ac-3 ? or mpeg encoders, may not adh ere to this convention and the bit ma y not be properly set. the CS8422 aes3 receiver can detect such non-audio data through the use of an auto-detect modul e. the auto-detect module is similar to auto-detect softwa re used in cirrus logic dsps. if the aes3 stream contains sync codes in the proper format for iec61937 or dts ? data transmission, an internal autodetect signal will be asserted. if the sync codes no longer appear after a certain amount of time, auto-detection will time-out and autodetect will be de-asserted until another format is detected. the audio signal is the logical or of autodetect and the received channel status bit 1. in software mode audio is available through the gpo pins. if no n-audio data is detected, the data is still processed exactly as if it were no rmal audio. the exceptio n is the use of de-emphasis auto-select feature which will bypass the de-emphasis filter if the input stream is detected to be non-audi o. it is up to the user to mute the outputs as required.
34 ds692pp2 CS8422 6.7.1 hardware mode control in hardware mode, audio is output on the v/audio pin when a 20 k resistor is connected from the v/audio pin to vl. 6.7.2 software mode control in software mode, the audio signal is available through the gpo pins. see ?gpo control 1 (05h)? on page 50 for more details. 6.8 format detection (software mode only) in software mode, the CS8422 can automatically detect various serial audio input formats. the format de- tect status register (12h) is used to indicate a de tected format. the register will indicate if uncompressed pcm data, iec61937 data, dts_ld data, dts_cd data, or digital silence was detected. additionally, the iec61937 pc/pd burst preambles are available in regist ers 2dh-30h. see the regist er descriptions for more information. 6.9 interrupts (software mode only) the int signal, available in software mode, indicate s when an interrupt condition has occurred and may be output on one of the gpos. it can be set through bits int[ 1:0] in the control1 regist er (02h) to be active low, active high, or open-drain active low. this last mode is used for active low, wir ed-or hook-ups, with multiple peripherals connected to the mi crocontroller interrupt input pin. many conditions can cause an interrupt, as listed in t he interrupt status register descriptions. each source may be masked off through mask regist er bits. in addition, some sources may be set to rising edge, falling edge, or level sensitive. combined with the option of level sensitive or edge sens itive modes within the mi- crocontroller, many different configurations are po ssible, depending on the needs of the equipment design- er. refer to the register descriptions for the interrup t unmasking (0fh), interrupt mode (10h), and interrupt status (14h) registers 6.10 channel status and user data handling ?channel status buffer management? on page 66 describes the overall handling of channel status and user data. 6.10.1 hardware mode control in hardware mode, received channel status (c), and user (u) bits are output on the c and tx/u pins (u data output must be selected on the tx/u pin, see ?hardware mode control? on page 39 for details). olrck2 and rcbl are made available to qualify the c and u data output. figure 19 illustrates timing of the c and u data and their related signals. 6.10.2 software mode control in software mode, several options are available for accessing the channel status and user data that is encoded in the received aes3 or spdif data. the first option allows access directly through register s. the first 5 bytes of the channel status block are decoded into the ?channel status registers (23h - 2ch)? . registers 23h-27h contain the a channel status data. registers 28h-2ch contain the b channel status data. received channel status (c), user (u), and emph bits may also be serial outputs to the gpo pins by appropriately setting the gpoxsel bits in the ?gpo control 1 (05h)? registers. olrck and rcbl can be
ds692pp2 35 CS8422 made available to qualify the c and u data output. in serial port slave mode, vlrck and rcbl can be made available to qualify the c and u data output. vl rck is a virtual word clock, equal to the receiver recovered sample rate, that can be used to frame the c/u output. vlrck and rcbl are available through the gpo pins. figure 19 illustrates timing of the c and u data, and thei r related signals. to recover serial c-data or u-data with either olrck1 or olrck2, the co rresponding serial port must be directly sourced by the aes3 receiver (not the src). to source an sdout signal directly from the rx rece iver, the receiver should be set in master mode in order to recover the received data. in this configuration, the sdout si gnal sourced from the receiver will toggle at the aes frame rate. if the rx receiver is set to sl ave mode, the user must ensure that its asso- ciated input olrck signal is externa lly synchronized to the input s/pdif stream in order to recover the received data. in both configurations, vlrck is equal to the olrck signal associated with the serial port used to clock the reco vered receiver data. when both sdouts are sourced from the rx receiver, vlrck will equal olrck1. when both sdouts are sourced from the src, then vlrck will equal the recovered aes frame rate, not olrck. the user may also access all of the c and u bits dire ctly from the output data stream (sdout) by setting bits sofselx[1:0]=11 (aes3 direct mode) in ?serial audio output data format - sdout1 (0ch)? or ?se- rial audio output data format - sdout2 (0dh)? . the appropriate bits can be stripped from the sdout signal by external co ntrol logic such as a dsp or microcontroller. aes3 direct mode is only valid if the serial port in question is directly s ourced by the aes3 rece iver (not the src). if the incoming user data bits have been encoded as q-channel subcode, t he data is decoded, buffered, and presented in 10 consecutive register locations located in ?q-channel subcode (19h - 22h)? register. an interrupt may be enabled to indicate the decoding of a new q-channel block, which may be read through the ?interrupt status (14h)? register. the encoded channel status bits which indicate sample word length are decoded according to aes3-2003 or iec 60958. th e number of auxiliary bits are re ported in bits 7 through 4 of the ?receiver channel status (11h)? . sdout1 sdout2 vlrck comment rx rx olrck1 see (note 4) rx src olrck1 see (note 4) src rx olrck2 see (note 4) src src aes frames see (note 6) table 1. vlrck behavior
36 ds692pp2 CS8422 rcbl (out) vlrck (out) c/u (out) c/u[0] c/u[1] c/u[383] t t 192 aes3 frames figure 19. c/u data outputs note: 1. rcbl will go high on the transition of the first output c/u data bit (c/u[0]) and will remain high until the c/u[0] - c/u[1] transition. 2. vlrck is a virtual word clock that is available through the gpo pins, and can be used to frame the c/u output. 3. vlrck frequency is always equal to the incoming frame rate of the aes3-compatible data. if there are an even number of osclk periods per olrck, then the vlrck duty cycle is 50%, otherwise it is 50% one osclk period. 4. if a serial audio output port is sourced direct ly by the aes3-compatible receiver vlrck = olrck in i2s mode, and vlrck = olrck in left-justified and right-justified modes. 5. if a serial port is sourced directly by the aes3-compatible receiver, the data will transition on the fourth osclk falling ed ge after a vlrck edge and will be valid on vlrck edges (t = 4 osclk period). 6. if a serial port is not sourced directly by the aes3-compatible receiver (as in a sample rate conversion application), the da ta will transition 1/64*fsi after a vlrck edge, and will be valid on vlrck edges (t = 1/64*fsi).
ds692pp2 37 CS8422 7. sample rate converter (src) multirate digital signal processing techniques are used to conceptually upsample the incoming data to a very high rate and then downsample to the outgoing rate. internal filtering is designed so that a full input audio bandwidth of 20 khz is preserved if the input sample and output sample rates are greater than or equal to 44.1 khz. when the output sample rate becomes less than the input sample rate , the input is automatically band limited to avoid aliasing artifacts in the output signal. any jitter in the incoming signal has little impact on the dynamic performance of the rate converter and has no influence on the output clock. 7.1 src data resolution and dither when using the serial audio input port in left justified and i2s modes, all input data is treated as 24-bits wide. any truncation that has been done prior to the CS8422 to less than 24-bits should have been done using an appropriate dither ing process. if the serial audi o input port is in right-justi fied mode, the input data will be truncated to the bit depth set through the ?serial audio input data format (0bh)? register. if the bit depth is set to 16 bits, and the input data is 24-bits wide, then trunc ation distortion will occur. similarly, in any serial audio input port mode, if an inadequate number of bit clocks are entered (i.e. 16 clocks instead of 20 clocks), then the input words will be truncate d, causing truncation distortion at low levels. in summary, there is no dithering mechanism on the input side of the CS8422, a nd care must be taken to ensure that no truncation occurs. the output side of the src can be set to 16, 18, 20, or 24. dithering is applied and is automatically scaled to the selected output word length. this dither is not correlated between left and right channel. 7.1.1 hardware mode control in hardware mode, the src is the da ta source for sdout1, and its serial output port data resolution is controlled through the saof pin. see section 8.1 on page 40 for more details. 7.1.2 software mode control in software mode, the serial port data resolution is controlled through the ?serial audio input data format (0bh)? , ?serial audio output data format - sdout1 (0ch)? , and ?serial audio output data format - sdout2 (0dh)? registers. 7.2 src locking the src calculates the ratio between the input sample rate and the output sample rate, and uses this in- formation to set up various parameters inside the s rc block. the src takes some time to make this cal- culation (approximately ~100 ms when fso = 48 khz). the src_unlock signal is used to indica te when the src is not locked. when rst is asserted, or if there is a change in fsi or fso, src_unlock will be set high. the src_unlock pin will continue to be high until the src has reacquired lock and se ttled, at which point it will tran sition low. when the src_unlock pin is set low, sdout is outputting valid audio data. this can be used to signal a dac to unmute its output. the src_unlock signal is available through the cont rol port register 15h, or through the src_unlock pin in hardware mode.
38 ds692pp2 CS8422 7.3 src muting the sdout pin sourced by the src (sdout1 or sdout2 in software mode, sdout1 in hardware mode) is set to all zero output (full mute) immediately after the rst pin is set high. while the output from the src becomes valid, sdout will be unmuted over a pe riod of approximately 40 96/fso (soft unmuted). when the output becomes invalid the src?s sdout is immediately set to all zero output (hard muted). after all invalid states have been clear ed, the src will soft unmute sdout. 7.4 src master clock the CS8422 can use the clock signal supplied through xti-xto, the pll, or an internal ring oscillator as its master clock (mclk). if the src mclk source is se lected as being xti-xto, care must be taken to en- sure that the src mclk source does not exceed 33 mhz. if the src mclk source exceeds 33 mhz, an internal clock divider can be enabled to divide the sr c mclk source by 2, allowing the use of higher fre- quency clocks. see section 7.4.1 and section 7.4.2 for more details. if the src mclk is applied through xti then it can be supplied from a digital clock source, a crystal oscil- lator, or a fundamental mode crystal. if xto is not used, such as with a digital clock source or crystal oscil- lator, xto should be left unconnected or pulled low through a 20 k resistor to gnd. if a crystal in conjunction with the in ternal oscillator is used to suppl y the src mclk, the crystal circuit should be connected as shown in figure 20 . if vl < 2.5 volts, it is recommended that the crystal attached across xti and xto should be specified as operatin g with a load capacitance of 10 pf (capacitors in figure 20 should be 20 pf). if vl 2.5 volts, it is recommended that the crystal attached across xti and xto should be specified as operating with a seri es capacitance of at 20 pf (capacitors in figure 20 should be at 40 pf). please refer to the crystal manufactur er?s specifications for more information about external capacitor recommendations. if the pll clock is selected as the src mclk, the src mclk will be synchronous to incoming aes3-com- patible data or isclk. unlike rmck, the user does not control pll clock?s relation ship to the sampling rate of incoming aes3-compatible da ta (fsi), or isclk. see table 2 for the relationship between the fsi or is- clk/64, and the pll clock. the CS8422 has the ability to operate without a master clock input through xti. this benefits the design by not requiring extra external clock components (loweri ng production cost) and not requiring a master clock to be routed to the CS8422, resulting in lowered noise contribution in the system. in this mode, an internal oscillator provides the clock to r un all of the internal logic. see section 7.4.1 and section 7.4.2 for explana- tion of how the src mclk can be selected. fsi (or isclk/64) pll/fsi fsi 49 khz 512 60 khz fsi 98 khz 256 120 khz fsi 128 table 2. pll clock ratios xti xto cc figure 20. typical connecti on diagram for cr ystal circuit
ds692pp2 39 CS8422 7.4.1 hardware mode control in hardware mode, the default master clock source for the src is the in ternal ring osc illator. therefore, it is not necessary to apply an exte rnal mclk source for the src. optionally the user may select the pll clock as the src mclk s ource by connecting a 20 k pull-up resistor between mclk_out and vl. 7.4.2 software mode control in software mode, the src master clock source is selected by the src_mclk[1:0] bits in the ?src out- put serial port clock control (08h)? register. if the xti clock is selected as the src mclk and xti is tied to vl or dgnd and xto is left un connected, then the internal ring os cillator will take the place of the xti- xto clock source. if the selected src mclk source is xti-xto, and is greater that 33 mhz, the user can enable the internal clock divide-by-two by setting the src_di v bit in control port register 08h. see ?src output serial port clock control (08h)? on page 51 for more details. 8. hardware mode control the CS8422 provides a stand-alone hardware control mode in which the part does not require an i2c or spi control port. in hardware mode, the user is provided with a subset of the features available in software mode as shown in figure 21 . the part will be in hardware mode if there is a 20 k pull-up resistor connected between the c pin and vl upon reset. controlling the CS8422 in hard ware mode is done through de dicated control inputs, 20 k pull-up or pull-down re- sistors attached to dual-purpose pins, and by attaching a sp ecific resistor values from one of two dedicated control pins (saof and ms_sel) to either vl or ground. in the case of saof and ms_sel, the resistor should be con- nected as close to the pin as possible and should ha ve a tolerance no greater than 1%. dedicated controls (tx_sel and rx_sel) can be changed during operation whereas pull-up resistor controls are sensed on startup. figure 21 shows clock routing options available in hardware mode. control signal names are in italics and are de- scribed in the table below. rxp/rxn0 rxp/rxn1 receiver clock recovery (pll) sample rate converter serial audio output 2 olrck1 osclk1 sdout1 tdm_in1 olrck2 osclk2 sdout2 serial audio output 1 2 2 rx_sel tx_sel tx ring oscillator (rmck pull-up) 2:1 mux (mclk_out pull-up) clock generator xti xto mclk_out 2:1 mux 2:1 mux ms_sel saof ms_sel saof rmck 2:1 mux figure 21. hardware mode clock routing
40 ds692pp2 CS8422 table 3. hardware mode control settings 8.1 hardware mode serial audio port control the CS8422 uses the resistors attached to the ms_sel and saof pins to determine the modes of opera- tion for its serial output ports. after a rst is asse rted, the resistor value and condition (vl or gnd) are sensed. this operation will take approximately 4 ms to complete. th e src_unlock pin will remain high and both sdout pins will be muted unt il the mode detectio n sequence has co mpleted. after this, if all clocks are stable, src_unlock will be brought low when au dio output is valid and no rmal operation will begin. the resistor attached to each mode selection pin should be placed physi cally close to the CS8422. the end of the resistor not connected to the mode selection pins should be connected as close as possible to vl and gnd to minimize noise. table 4 and table 5 show the pin functions and their corresponding settings. table 4 shows the hardware mode options for output serial port format and the required saof pin config- urations. in the case of sdout2, th e output resolution d epends on the re solution of the incoming aes3- compatible data. in right-jus tified modes, the serial format word-l ength will be equal to the aes3 input data resolution. the exception is the ca se where right-justified mode is selected and the aes3 input word- length is an odd number of bits. in this case, the sdout2 word-l ength will be zero-stuffed to be 1 bit longer then the aes3 input word-l ength (example: a 19-bit aes3 input word will result in an 20-bit right-justified serial format). for a more detailed description of serial formats, refer to section 5. on page 24 . table 5 shows the hardware mode master/slave and clock options for both serial ports, and the required ms_sel pin configurations. for sdout1, when the serial port is set to master mode, the master clock ratio pin name description pin configuration selection rx_sel selects active aes3 rx input connected to gnd rxp0/rxn0 is active connected to vl rxp1/rxn1 is active tx_sel selects rx input to be output on tx pin connected to gnd rxp0/rxn0 to tx connected to vl rxp1/rxn1 to tx sdout1 enables or disables de-emphasis auto-detect no pull-up on sdout1 de-emphasis auto-detect enabled 20 k pull-up on sdout1 de-emphasis auto-detect disabled saof selects data format for sdout1 & sdout2 see table 4 on page 41 ms_sel selects master/slave and clock configuration for sdout1& sdout 2 see table 5 on page 41 rmck selects master clock source for sdout1 serial port no pull-up on rmck xti-xto 20 k pull-up on rmck rmck mclk_out selects master clock source for the src no pull-up on mclk_out ring oscillator 20 k pull-up on mclk_out pll clock tx/u selects tx pass-through output or incoming u data output no pull-up on u tx pass-through 20 k pull-up on u u data output c selects software or hardware mode no pull-up on c software mode 20 k pull-up on c hardware mode nv/rerr selects error signal output on nv/rerr no pull-up on rerr/nverr nverr 20 k pull-up on rerr/nverr rerr v/audio selects either incoming validity data output or audio indicator output 20 k pull-down on v/audio validity data output 20 k pull-up on v/audio audio indicator output
ds692pp2 41 CS8422 determines what the output sample rate will be based on the mclk sele cted for sdout1, as shown in the hardware control pin descriptions shown above. for sdou t2, the output sample rate is dictated by the in- coming aes3 data, and the ma ster mode clock ratio determines the fr equency of rmck relative to the in- coming aes3 sample rate. note: if tdm mode is selected for sdout1, then sdout1 cannot be set to ?master, fso = mclk/128?. saof pin sdout1 data format sdout2 data format 32.4 k 1% to gnd i2s 24-bit data i2s 16.2 k 1% to gnd i2s 20-bit data i2s 8.06 k 1% to gnd i2s 16-bit data i2s 4.02 k 1% to gnd left-justified 24-bit data left-justified 1.96 k 1% to gnd left-justified 20-bit data left-justified 1.0 k + 1% to gnd left-justified 16-bit data left-justified 32.4 k 1% to vl right-justified 24-bit data (master mode only) right-justified (master mode only) 16.2 k 1% to vl right-justified 20-bit data (master mode only) right-justified (master mode only) 8.06 k 1% to vl right-justified 16-bit data (master mode only) right-justified (master mode only) 4.02 k 1% to vl tdm mode 24-bit data i2s 1.96 k 1% to vl tdm mode 20-bit data i2s 1.0 k + 1% to vl tdm mode 16-bit data i2s table 4. hardware mode serial audio format control ms_sel pin sdout1 sdout2 127.0 k 1% to gnd slave slave rmck = 256 x fsi 63.4 k 1% to gnd master, fso = mclk/128 32.4 k 1% to gnd master, fso = mclk/256 16.2 k 1% to gnd master, fso = mclk/512 8.06 k 1% to gnd slave master mode, rmck = 128 x fsi 4.02 k 1% to gnd master, fso = mclk/128 1.96 k 1% to gnd master, fso = mclk/256 1.0 k + 1% to gnd master, fso = mclk/512 127.0 k 1% to vl slave master mode, rmck = 256 x fsi 63.4 k 1% to vl master, fso = mclk/128 32.4 k 1% to vl master, fso = mclk/256 16.2 k 1% to vl master, fso = mclk/512 8.06 k 1% to vl slave master mode, rmck = 512 x fsi 4.02 k 1% to vl master, fso = mclk/128 1.96 k 1% to vl master, fso = mclk/256 1.0 k + 1% to vl master, fso = mclk/512 table 5. hardware mode seri al audio port clock control
42 ds692pp2 CS8422 9. software mode control 9.1 control port description the control port is used to access the registers, allo wing the CS8422 to be configured for the desired oper- ational modes and formats. the operation of the contro l port may be completely asynchronous with respect to the audio sample rates. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port has two modes: spi and i2c, with th e CS8422 acting as a slave device. spi mode is se- lected if there is a high to low transition on the ad0/cs pin, after the rst pin has been brought high. i2c mode is selected by connecting the ad0/cs pin through a resistor to vl or dgnd, thereby permanently selecting the desired ad0 bit address state. 9.1.1 spi mode in spi mode, cs is the CS8422 chip select signal, cclk is t he control port bit clock (input into the CS8422 from the microcontroller), cdin is the input data line from the microcontroller, cdout is the output data line to the microcontroller. data is clocked in on the rising edge of cclk and out on the falling edge. figure 22 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and mu st be 0010000. the eighth bit is a read/write indi- cator (r/w ), which should be low to write. the next eight bits include the 7-bit memory address pointer (map), which is set to the address of the register that is to be updated. the ne xt eight bits are the data which will be placed into the regist er designated by the map. during writes, th e cdout output stays in the hi-z state. it may be externally pulled high or low with a 20 k resistor, if desired. to read a register, the map has to be set to the co rrect address by executing a partial write cycle which finishes (cs high) immediately after the map byte. to begin a read, bring cs low, send out the chip ad- dress and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leav e the high impedance state). the map automat ically increments, so data for successive regist ers will appear consecutively. map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 0010000 0010000 map = memory address pointer, 8 bits, msb first high impedance figure 22. control port timing in spi mode
ds692pp2 43 CS8422 9.1.2 i2c mode in i2c mode, sda is a bidirectional da ta line. data is clocked into and out of the part by the clock, scl. there is no cs pin. pins ad0 and ad1 form the two least signi ficant bits of the chip address and should be connected to vl or dgnd as desired. the gpo2 pin is used to set the ad2 bit by connecting a 20 k resistor from the gpo2 pin to vl (a 20 k pull-up sets ad2 = 1, and the absence of a pull-up sets ad2 = 0). the states of the pins are sensed while the CS8422 is being reset. the signal timings for a read and write cycle are shown in figure 23 and figure 24 . a start condition is defined as a falling transition of sda while the clock is high. a stop co ndition is a rising transition while the clock is high. all other transitions of sda occur while the clock is low. the first byte sent to the CS8422 after a start condition consists of a 7-bit chip address field and a r/w bit (high for a read, low for a write). the upper 4 bits of the 7-bit address field are fixed at 0010. to communicate with a CS8422, the chip address field, which is the first byte s ent to the CS8422, should match 0010 followed by the settings of the ad2, ad1, and ad0 pins. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte in cludes the memory address pointer (map) which se- lects the register to be read or written. if the operatio n is a read, the contents of the register pointed to by the map will be output. each byte is separated by an acknowledge bit (ack). the ack bit is output from the CS8422 after each input byte is read, and is input to the CS8422 from the microcontroller after each transmitted byte. note that the read operation can not set the map so an aborted write operation is used as a preamble. as shown in figure 24 , the write operation is aborted after the acknowledge for the map byte by sending a stop condition. 9.1.3 memory address pointer (map) the map is an 8-bit word containing the control port addr ess to be read or written in both spi and i2c modes and a bit to control an auto-increment feature. map[6:0] constitute the address to be read or written, while bit 7 of the map (inc) determines wh ether or not map[6:0] will automati cally increment after each control port read or write. if inc = 0, map[ 6:0] will not automatically increment afte r each control port read or write. if inc = 1, map[6:0] will automatica lly increment after each control port read or write. the map byte is shown in figures 23 and 24 . 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 0 0 1 0 ad2 ad1 ad0 0 sda 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n inc figure 23. control port timing, i2c slave mode write scl chip address (write) map byte data data +1 start ack stop ack ack ack sda chip address (read) start 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop 0 0 1 0 ad2 ad1 ad0 0 0 0 1 0 ad2 ad1 ad0 1 inc figure 24. control port timing, i2c slave mode read
44 ds692pp2 CS8422 10.register quick reference this table shows the register names and default values for read-write registers. addr function 7 6 5 4 3 2 1 0 01h chip id & version id4 id3 id2 id1 id0 rev2 rev1 rev0 00010000 02h clock control pdn fswclk swclk rmck_ ctl1 rmck_ ctl0 int1 int0 reserved 10000000 03h receiver input control rx_mode rxsel1 rxsel0 txsel1 txsel0 input_ type reserved reserved 00001000 04h receiver data control trunc hold1 hold0 chs detci emph_ cntl2 emph_ cntl1 emph_ cntl0 00000100 05h gpo control 1 gpo0sel3 gpo0sel2 gpo0sel1 gpo0sel0 gpo1sel3 gpo1sel2 gpo1sel1 gpo1sel0 00000000 06h gpo control 2 gpo2sel3 gpo2sel2 gpo2sel1 gpo2sel3 gpo3sel2 gpo3sel1 gpo3sel0 gpo3sel3 00000000 07h sai clock con- trol sai_clk3 sai_clk2 sai_clk1 sai_clk0 sai_mclk reserved reserved reserved 01000000 08h src sao clock control sao_clk3 sao_clk2 sao_clk1 sao_clk0 sao_ mclk src_ mclk1 src_ mclk2 src_div 01100000 09h rmck cntl.& misc. rmck3 rmck2 rmck1 rmck0 src_ mute reserved reserved reserved 00001000 0ah data routing control sdout1_1 sdout1_0 sdout2_1 sdout2_0 mute_ sao1 mute_ sao2 srcd reserved 00010000 0bh sai data format sims sisf sifsel2 sifsel1 sifsel 0 reserved reserved reserved 00000000 0ch sao1 data for- mat & tdm soms1 sosf1 sores1_1 sores1_0 sofsel1_1 sofsel1_0 tdm1 tdm0 00000000 0dh sao2 data for- mat soms2 sosf2 sores2_1 sores2_0 sofsel2_1 sofsel2_0 reserved reserved 00000000 0eh rerr unmask- ing activem qcrcm ccrcm unlockm vm confm bipm parm 00000000 0fh interrupt unmasking pcchm oslipm detcm cchm rerrm qchm fchm src_ unlockm 00000000 10h interrupt mode reserved reserved reserved reserved rerr1 rerr0 src_ unlock1 src_ unlock0 00000000 table 6. summary of so ftware register bits
ds692pp2 45 CS8422 11h receiver chan- nel status aux3 aux2 aux1 aux0 pro copy orig emph 12h format detect status pcm iec61937 dts_ld dts_cd hd_cd dgtl_sil reserved reserved 13h receiver error active qcrc ccrc unlock v conf bip par 14h interrupt status pcch oslip detc cch rerr qch fch src_ unlock 15h pll status rx_ active isclk_ active pll_lock 96khz 192khz reserved reserved reserved 16h receiver status cs_ update rcvr_ rate1 rcvr_ rate0 rx_lock blk_verr blk_cerr blk_berr blk_perr 0 17h fs/xti ratio 1 fs_xt15 fs_xt14 fs_xt13 fs_xt12 fs_xt11 fs_xt10 fs_xt9 fs_xt8 18h fs/xti ratio 2 fs_xt7 fs_xt6 fs_xt5 fs_xt4 fs_xt3 fs_xt2 fs_xt1 fs_xt0 19h q subcode 1 control control control control address address address address 1ah q subcode 2 track track track track track track track track 1bh q subcode 3 index index index index index index index index 1ch q subcode 4 minute minute minute minute minute minute minute minute 1dh q subcode 5 second second secon d second second second second second 1eh q subcode 6 frame frame frame frame frame frame frame frame 1fh q subcode 7 zero zero zero zero zero zero zero zero 20h q subcode 8 abs minute abs minute abs minute abs minute abs minute abs minute abs minute abs minute 21h q subcode 9 abs second abs second abs second abs second abs second abs second abs second abs second 22h q subcode 10 abs frame abs frame abs frame abs frame abs frame abs frame abs frame abs frame 23h channel a sta- tus byte 0 ac0[7] ac0[6] ac0[5] ac0[4] ac0[3] ac0[2] ac0[1] ac0[0] 24h channel a sta- tus byte 1 ac1[7] ac1[6] ac1[5] ac1[4] ac1[3] ac1[2] ac1[1] ac1[0] 25h channel a sta- tus byte 2 ac2[7] ac2[6] ac2[5] ac2[4] ac2[3] ac2[2] ac2[1] ac2[0] 26h channel a sta- tus byte 3 ac3[7] ac3[6] ac3[5] ac3[4] ac3[3] ac3[2] ac3[1] ac3[0] 27h channel a sta- tus byte 4 ac4[7] ac4[6] ac4[5] ac4[4] ac4[3] ac4[2] ac4[1] ac4[0] 28h channel b sta- tus byte 0 bc0[7] bc0[6] bc0[5] bc0[4] bc0[3] bc0[2] bc0[1] bc0[0] 29h channel b sta- tus byte 1 bc1[7] bc1[6] bc1[5] bc1[4] bc1[3] bc1[2] bc1[1] bc1[0] 2ah channel b sta- tus byte 2 bc2[7] bc2[6] bc2[5] bc2[4] bc2[3] bc2[2] bc2[1] bc2[0] 2bh channel b sta- tus byte 3 bc3[7] bc3[6] bc3[5] bc3[4] bc3[3] bc3[2] bc3[1] bc3[0] addr function 7 6 5 4 3 2 1 0 table 6. summary of software register bits (continued)
46 ds692pp2 CS8422 2ch channel b sta- tus byte 4 bc4[7] bc4[6] bc4[5] bc4[4] bc4[3] bc4[2] bc4[1] bc4[0] 2dh burst preamble pc byte 0 pc0[7] pc0[6] pc0[5] pc0[4] pc0[3] pc0[2] pc0[1] pc0[0] 2eh burst preamble pc byte 1 pc1[7] pc1[6] pc1[5] pc1[4] pc1[3] pc1[2] pc1[1] pc1[0] 2fh burst preamble pd byte 0 pd0[7] pd0[6] pd0[5] pd0[4] pd0[3] pd0[2] pd0[1] pd0[0] 30h burst preamble pd byte 1 pd1[7] pd1[6] pd1[5] pd1[4] pd1[3] pd1[2] pd1[1] pd1[0] addr function 7 6 5 4 3 2 1 0 table 6. summary of software register bits (continued)
ds692pp2 47 CS8422 11.software register bit definitions the table row beneath the row t hat contains the register-bit name shows the register bit default value. bits labeled ?reserved? must remain at their default value. 11.1 CS8422 i.d. and version register (01h) id [4:0] - id code for the CS8422. permanently set to 00010 rev [2:0] = 000 (revision a) rev [2:0] = 010 (revision b1) 11.2 clock control (02h) pdn - controls the internal clocks, allowing the CS8422 to be placed in a ?powered down?, low current con- sumption state. this bit must be written to the 0 stat e to allow the CS8422 to begin operation. all input clocks should be stable in frequency and phase when pdn is set to 0. 0- normal part operation. 1- internal clocks are stopped. intern al state machines are reset. the fully static control port is operational, allowing registers to be read or changed. power consumption is low. fswclk ? forces the clock signal on xti to be output on rmck regardless of the swclk bit functionality or pll lock. 0 ? clock signal on xti is output on rmck according to the swclk bit functionality. 1 ? forces the clock signal on xti to be output on rmck regardless of the swclk bit functionality. swclk - outputs xti clock signal on rmck pin when pll loses lock. any osclk or olrck derived from rmck under normal conditions will be derived from xti in this case. 0 - disable automatic clock switching. 1 - enable automatic clock switching on pll unlock. cl ock signal selected on xti is automatically output on rmck on pll unlock. rmck_ctl[1:0] - rmck control 00 - rmck is an output and is derived fr om the frame rate of incoming aes3 data. 01 - rmck is an output and is derived from the iscl k input frequency divided by 64. only valid if serial audio input port is in slave mode (sims = 0 in ?serial audio input data format (0bh)? on page 53 ). 10 - rmck is high-impedance. 11 - reserved int[1:0] - interrupt output pin (int) control 00 - active high; high output indica tes interrupt condition has occurred. 76543210 id4 id3 id2 id1 id0 rev2 rev1 rev0 00010000 76543210 pdn fswclk swclk rmck_ctl1 rmck_ctl0 int1 int0 reserved 10000000
48 ds692pp2 CS8422 01 - active low, low outp ut indicates an interrup t condition has occurred. 10 - open drain, active low. requires an external pull-up resistor on the int pin. 11 - reserved. 11.3 receiver input control (03h) rx_mode - selects the input mode (single-ended or differential) of the rx pins 0 - receiver inputs are differential-pair inputs rxp1/rxn1 and rxp0/rxn0. 1 - receiver inputs are single-ended inputs rx[3:0]. rx_sel [ 1:0] ? input multiplexer to the receiver 00 - rx0 or rxp0/rxn0 01 - rx1 (only valid if rx_mode = 1) 10 - rx2 or rxp1/rxn1 11 - rx3 (only valid if rx_mode = 1) tx_sel[1:0] ? selects receiver input for gpo tx source 00 - rx0 or rxp0/rxn0 01 - rx1 (only valid if rx_mode = 1) 10 - rx2 or rxp1/rxn1 11 - rx3 (only valid if rx_mode = 1) input_type ? selects receiver input type 0 - mode 1, receiver multiplexer inputs are comparator inputs biased at va/2. 1 - mode 2, receiver multiplexer inputs are digital inputs, referenced to va. valid only if rx_mode = 1. 11.4 receiver data control (04h) trunc ? determines if the audio word length is set acco rding to the incoming channel status data as de- coded by the aux[3:0] bits. the resulting wo rd length in bits is 24 minus aux[3:0]. 0 ? incoming data is not truncated. 1 ? incoming data is truncated according to the length specified in the channel status data. truncation occurs before the de-emphasis filter. trunc has no effect on output data is detected as being non-audio. hold[1:0] ? determine how received aes3 audio sample is affected when a receive error occurs 00 - hold last audio sample. 76543210 rx_mode rxsel1 rxsel0 txsel1 txsel0 input_type reserved reserved 00010000 76543210 trunc hold1 hold0 chs detci emph_cntl2 emph_cntl1 emph_cntl0 00000100
ds692pp2 49 CS8422 01 - replace the current audio sample with all zeros (mute). 10 - do not change the received audio sample. 11 - reserved chs ? sets which channel's c data is decoded in the re ceiver channel status register (11h) (default = ?0?) 0 - a channel 1 - b channel if chs = 0 and trunc = 1, both channels' audio data will be truncated by the aux[3:0] bits indicated in the channel a channel status data. if chs = 1 a nd trunc = 1, both channels' audio data will be trun- cated by the aux[3:0] bits indica ted in the channel b channel status data. this will occur even if the aux[3:0] bits indicated in the channel a channel status data are not equal to the aux[3:0] bits indicated in the channel b channel status data. detci - d to e status transfer inhibit 0 -allow update 1 -inhibit update dem_cntl[2:0] ? de-emphasis filter control. see figure 25 for de-emphasis filter response. 000 - de-emphasis filter off. 001 - 32 khz setting 010 - 44.1 khz setting 011 - 48 khz setting 100 - auto-detect sample rate. if the pll estimates that the incoming sample rate is below 49 khz, de- emphasis will be applied acco rding to the channel stat us data of the incoming aes3 or s/pdif data. if the pll estimates that the incoming sample rate is not below 49 khz, de-emphasis will not be enabled. if the incoming channel status data indicates that no de-emphasis shou ld be applied, de-emphasis will not be enabled. if data is detected as being non-audio, the de -emphasis filter will not be enabled. figure 25. de-emphasis filter response gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz
50 ds692pp2 CS8422 11.5 gpo control 1 (05h) gpoxsel[3:0] ? gpo source select for gpo0 and gpo1 pins. see table 7 for available outputs for gpo[3:0]. 11.6 gpo control 2 (06h) gpoxsel[3:0] ? gpo source select for gpo2 and gpo3 pins. see table 7 for available outputs for gpo[3:0]. 11.7 serial audio input clock control (07h) sai_clk[3:0] ? selects the serial audio input master clock- to-ilrck ratio when the serial audio input port is set to master mode (sims = 1 as shown in ?serial audio input data format (0bh)? on page 53 ). note: if a serial audio output is sourced directly by the serial audio input port, sai_clk[3:0] determine the mclk/lrck ratio for both serial port s if they are set to master mode. 0000 - ilrck = mclk/64 7 6 543210 gpo0sel3 gpo0sel2 gpo0sel1 gpo0sel0 g po1sel3 gpo1sel2 g po1sel1 gpo1sel0 0 0 000000 7 6 543210 gpo2sel3 gpo2sel2 gpo2sel1 gpo2sel0 g po3sel3 gpo3sel2 g po3sel1 gpo3sel0 0 0 000000 function code definition gnd 0000 fixed low level vl 0001 fixed vl level. emph 0010 state of emph bit in the incoming data stream int 0011 CS8422 interrupt output c 0100 channel status bit u 0101 user data bit rerr 0110 receiver error nverr 0111 non-validity receiver error rcbl 1000 receiver channel status block 96khz 1001 defined in ?pll status (15h)? on page 60 . 192khz 1010 defined in ?pll status (15h)? on page 60 . audio 1011 non-audio indicator for decoded input stream vlrck 1100 virtual lrck, can be used to frame the c and u output data. tx 1101 pass through of aes/spdif in put selected by txsel[2:0] in section 11.3 ?receiver input control (03h)? on page 48 . src_unlock 1110 src unlock indicator xti_out 1111 buffered xti-xto output table 7. gpo pin configurations 76543210 sai_clk3 sai_clk2 sai_clk1 sai_clk0 sai_mclk reserved reserved reserved 01000
ds692pp2 51 CS8422 0001 - ilrck = mclk/96 0010 - ilrck = mclk/128 0011 - ilrck = mclk/192 0100 - ilrck = mclk/256 0101 - ilrck = mclk/384 0110 - ilrck = mclk/512 0111 - ilrck = mclk/768 1000 - ilrck = mclk/1024 sai_mclk ? selects the master clock (mcl k) source for the serial audio input when set to master mode (sims = 1, as shown in ?serial audio input data format (0bh)? on page 53 ). when set to master, ilrck and isclk are derived from the mclk selected in this re gister. note: if either serial audio output port is sourced directly by the serial audio input port, this bit determines the master cl ock source for the selected serial output port when it is in master mode. 0 - xti-xto 1 - rmck 11.8 src output serial po rt clock control (08h) sao_clk[3:0] ? valid only for the serial port sourced by the src. selects the serial audio input master clock-to-olrck ratio when the serial audio output port is set to master mode (soms = 1 as shown in ?serial audio output data format - sdout1 (0ch)? on page 54 and ?serial audio output data format - sdout2 (0dh)? on page 55 ). 0000 - olrck = mclk/64 0001 - olrck = mclk/96 0010 - olrck = mclk/128 0011 - olrck = mclk/192 0100 - olrck = mclk/256 0101 - olrck = mclk/384 0110 - olrck = mclk/512 0111 - olrck = mclk/768 1000 - olrck = mclk/1024 sao_mclk ? selects the master clock (mclk) source fo r the serial audio output, sourced by the src, when set to master mode (soms1 or soms 2 = 1, as shown in ?serial audio output data format - sdout1 (0ch)? on page 54 and ?serial audio output data format - sdout2 (0dh)? on page 55 ). when set to mas- ter, olrck and osclk are derived from the mclk selected in this register. 0 - xti-xto 76543210 sao_clk3 sao_clk2 sao_clk1 sao_clk0 sao _mclk src_mclk1 src_mclk0 src_div 01000000
52 ds692pp2 CS8422 1 - rmck src_mclk[1:0] - controls the master clock (mclk) source for the sample rate converter. see ?src mas- ter clock? on page 38 for details. 00 - xti-xto. if xti is connected to gnd or vl and xto is left floatin g, the src mclk will be the internal ring oscillator. 01 - pll clock 10 - internal ring oscillator 11 - reserved src_div ? divide-by-two for the src mclk so urce. valid only if src_mclk = 00. 0 - src mclk is not divided. maximum allowable src mclk frequency is 33 mhz. 1 - src mclk is divided. maximum allo wable src mclk frequency is 49.152 mhz. 11.9 recovered master clock ra tio control & misc. (09h) rmck[3:0] ? selects the rmck/fsi ratio, where fsi is th e sample rate of the incoming aes3-compatible data or isclk/64. note: if a serial audio output port is in master mode and sourced di rectly by the aes3 receiver, then rmck is the master clock source for the selected serial output port and rmck[3:0] determine the mclk/olrck ratio for the se lected serial output port. 0000 - rmck = 64 x fsi 0001 - rmck = 96 x fsi 0010 - rmck = 128 x fsi 0011 - rmck = 192 x fsi 0100 - rmck = 256 x fsi 0101 - rmck = 384 x fsi 0110 - rmck = 512 x fsi 0111 - rmck = 768 x fsi 1000 - rmck = 1024 x fsi src_mute ? when src_mute is set to ?1?, the src will soft-mute when it loses lock and soft unmute when it regains lock. 0 - soft mute disabled 1 - soft mute enabled 11.10 data routing control(0ah) sdout1[1:0] - controls the data source for sdout1 76543210 rmck3 rmck2 rmck1 rmck0 src_mute reserved reserved reserved 00001 76543210 sdout1(1) sdout1(0) sd out2(1) sdout2(0) mutesao1 mutesao2 srcd reserved 0001000
ds692pp2 53 CS8422 00 - sample rate converter 01 - aes3 receiver output 10 - sdin (sdin and sdout should be synchronous) 11 - reserved sdout2[1:0] - controls the data source for sdout2 00 - sample rate converter 01 - aes3 receiver output 10 - sdin (sdin and sdout should be synchronous) 11 - reserved mutesao1 - mute control for the serial audio output port 1 0 - sdout1 not muted 1 - sdout1 muted (set to all zeros) mutesao2 - mute control for the serial audio output port 2 0 - sdout2 not muted. 1 - sdout2 muted (set to all zeros). srcd - controls the data source of the sample rate converter 0 - serial audio input port (sdin) 1 - aes3 receiver output 11.11 serial audio input data format (0bh) sims - master/slave mode selector 0 - serial audio input port is in slave mode. isclk and ilrck are inputs. 1 - serial audio input port is in master mode. isclk and ilrck are outputs. sisf - isclk frequency. valid only in master mode (sims = 1). should be changed when pdn = 1. see table 8 for details. 76543210 sims sisf sifsel2 sifsel1 sifsel 0 reserved reserved reserved 00000 sai_clk[3:0] mclk/ilrck ratio isclk/ilrck ratio sisf = 0 sisf = 1 0000 64 64 invalid 0001 96 48 96 0010 128 64 128 0011 192 48 96 0100 256 64 128 table 8. isclk/ilrck ra tios and sisf settings
54 ds692pp2 CS8422 sifsel[2:0] - serial audio input data format 000 - left-justified, up to 24-bit data 001 - i2s, up to 24-bit data 010 - right-justified, 24-bit data 011 - right-justified, 20-bit data 100 - right-justified, 18-bit data 101 - right-justified, 16-bit data 110, 111 - reserved 11.12 serial audio output da ta format - sdout1 (0ch) soms1 - master/slave mode selector 0 - serial audio output port is in slave mode. osclk and olrck are inputs. 1 - serial audio output port is in master mode. osclk and olrck are outputs. sosf1 - osclk1 frequency. valid only in master mode (soms1 = 1). if the src is selected as the source for sdout1 (sdout1[1:0] = 00 in register 0ah), t hen the master clock (mclk) is the sao mclk (as se- lected by the sao_mclk bit in register 08h). if the aes3 receiver is selected as the source for sdout1 (sdout1[1:0] = 01 in register 0ah), then the mclk is rmck. should be changed when pdn = 1. see table 9 for details. note: if serial output 1 is in master mode a nd sourced directly by the serial input port, sai_clk[3:0] determines the mclk/olrck1 ratio. 0101 384 48 96 0110 512 64 128 0111 768 48 96 1000 1024 64 128 76543210 soms1 sosf1 sores1_1 sores1_0 sofsel1_1 sofse l1_0 tdm1 tdm0 00000000 sao_clk[3:0], sai_clk[3:0], or rmck[3:0] mclk/olrck1 ratio osclk1/olrck1 ratio sosf1 = 0 sosf1 = 1 0000 64 64 invalid 0001 96 48 96 0010 128 64 128 0011 192 48 96 0100 256 64 128 0101 384 48 96 0110 512 64 128 0111 768 48 96 1000 1024 64 128 table 9. osclk1/olrck1 ra tios and so sf1 settings table 8. isclk/ilrck ratios and sisf settings
ds692pp2 55 CS8422 sores1[1:0] - resolution of the output data on sdout 00 - 24-bit resolution. 01 - 20-bit resolution. 10 - 18-bit resolution. 11 - 16-bit resolution sofsel1[1:0] - format of the output data on sdout 00 - left-justified 01 - i2s 10 - right-justified (master mode only) 11 - aes3 direct. direct copy of the received nrz data from the aes3 receiver including c, u, and v bits. the time slot occupied by the z bit is used to indicate th e location of the block start. only valid if serial port sourced directly by the aes3-compatible receiver. tdm [1:0] - enable the time-division mu ltiplexing (tdm) through tdm_in and either sdout1 or sdout2. see ?time division multiplexing (tdm) mode? on page 27 for more details. 00 - tdm mode not enabled. serial audio format selected by sofsel1[1:0] 01 - tdm mode enabled through tdm_in and sdout1 . sofsel1[1:0] has no effect in this mode. 10 - tdm mode enabled through tdm_in and sdout2 . sofsel2[1:0] has no effect in this mode. 11 - reserved 11.13 serial audio output da ta format - sdout2 (0dh) soms2 - master/slave mode selector 0 - serial audio output port is in slave mode. osclk and olrck are inputs. 1 - serial audio output port is in ma ster mode. osclk and olrck are outputs. sosf2 - osclk2 frequency. valid only in master mode (soms2 = 1). if the src is selected as the source for sdout2 (sdout2[1:0] = 00 in register 0ah), then the master clock (mclk) is the sao mclk (as se- lected by the sao_mclk bit in regi ster 08h). if the aes3 receiver is selected as the source for sdout2 (sdout2[1:0] = 01 in register 0ah), then the mc lk is rmck. should be changed when pdn = 1. see table 10 for details. note: if serial output 2 is in master mode and sourced directly by the serial input port, then sai_clk[3:0] determine the mclk/olrck1 ratio. 76543210 soms2 sosf2 sores2_1 sores2_0 sofsel 2_1 sofsel2_0 reserved reserved 000000 sao_clk[3:0], sai_clk[3:0], or rmck[3:0] mclk/olrck2 ratio osclk2/olrck2 ratio sosf2 = 0 sosf2 = 1 0000 64 64 invalid 0001 96 48 96 table 10. osclk2/olrck2 ra tios and sosf1 settings
56 ds692pp2 CS8422 sores2[1:0] - resolution of the output data on sdout 00 - 24-bit resolution. 01 - 20-bit resolution. 10 - 18-bit resolution. 11 - 16-bit resolution sofsel2[1:0] - format of the output data on sdout 00 - left-justified 01 - i2s 10 - right-justified (master mode only) 11 - aes3 direct. direct copy of the received nrz data from the aes3 re ceiver including c, u, and v bits. the time slot occupied by the z bit is used to indicate the location of the block star t. only valid if serial port source is the aes3-c ompatible receiver. 11.14 receiver error unmasking (0eh) receiver error mask[7:0] the bits[7:0] in this register serve as masks for the corresponding bits of the receiver error register. if a mask bit is set to 1, the error is unmasked, meaning that its occurrence will appear in the re ceiver error reg- ister, will affect rerr[6:0], will affect the rerr interr upt, and will affect the curren t audio sample according to the status of the hold bit. if a ma sk bit is set to 0, the error is ma sked, meaning that its occurrence will not appear in the receiver error regi ster, will not affect the rerr pin, will not affect the rerr interrupt, and will not affect the curr ent audio sample. the active, ccrc, and qcrc bits behave differently from the other bits: they do not affect th e current audio sample even when unmask ed. if qcrc, ccrc, conf, bip, or parm are unmasked, and rerrm in register 0fh is unmasked, then rerr[1:0] s hould be set to ?rising edge active? in the interrupt mode register (r egister 10h). this register defaults to 00h. 11.15 interrupt unmasking (0fh) the bits of this register serve as a mask for the interr upt status register. if a mask bit is set to 1, the error is unmasked, meaning t hat its occurrence will affect the int pin and the status register. if a mask bit is set 0010 128 64 128 0011 192 48 96 0100 256 64 128 0101 384 48 96 0110 512 64 128 0111 768 48 96 1000 1024 64 128 76543210 activem qcrcm ccrcm unlockm vm confm bipm parm 0000000 7654321 0 pcchm oslipm detcm cchm rerrm qchm fchm src_unlockm 0000000 0 table 10. osclk2/olrck2 ra tios and sosf1 settings
ds692pp2 57 CS8422 to 0, the error is masked, meaning th at its occurrence will not affect the in ternal int signal or the status reg- ister. the bit positions align with the corresponding bits in interrupt status register. this register defaults to 00h. the int signal may be selected to output on the gpo pins. see section 11.5 on page 50 for more details. 11.16 interrupt mode (10h) the interrupt mode control in the behavior of the int pin to rerr and src_unlock interrupts. there are three ways to set the int pin active in accordance wi th the interrupt condition. in the rising edge active mode, the int pin becomes active on the arrival of the interrupt condit ion. in the falling edge active mode, the int pin becomes active on the removal of the interr upt condition. in level ac tive mode, the int interrupt pin becomes active during the interrupt condition. be aware that the active level (active high or low) only depends on the int[1:0] bits. these registers default to 00h. the interrupts in the interrupt status register not represented here are all rising edge active. 00 - rising edge active 01 - falling edge active 10 - level active 11 - reserved 11.17 receiver channel status (11h) the bits in this register can be associated with eith er channel a or b of the received data. the desired chan- nel is selected with the chs bit of ?receiver data control (04h)? on page 48 . aux3:0 - incoming aux iliary data field width, as indicated by th e incoming channel status bits, decoded ac- cording to iec60958 and aes3. 0000 - auxiliary dat a is not present. 0001 - auxiliary data is 1 bit long. 0010 - auxiliary data is 2 bits long. 0011 - auxiliary data is 3 bits long. 0100 - auxiliary data is 4 bits long. 0101 - auxiliary data is 5 bits long. 0110 - auxiliary data is 6 bits long. 0111 - auxiliary data is 7 bits long. 1000 - auxiliary data is 8 bits long. 1001 - 1111 reserved pro - channel status block format indicator 0 - received channel status block is in the consumer format. 765432 1 0 reserved reserved reserved reserve d rerr1 rerr0 src_unlock1 src_unlock0 00 0 0 76543210 aux3 aux2 aux1 aux0 pro copy orig emph
58 ds692pp2 CS8422 1 - received channel status block is in the professional format. copy - scms copyright indicator 0 - copyright asserted. 1 - copyright not asserted. if the category code is set to general in the incoming aes3 stream, copyright will always be indicated by copy, even wh en the stream indicates no copyright. orig - scms generation indicator, decoded from the category code and the l bit. 0 - received data is 1st generation or higher. 1 - received data is original. note: copy and orig will both be set to 1 if incoming da ta is flagged as professi onal or if the receiver is not in use. emph ? indicates if the input channel status data indi cates that the incoming audio data has been pre-em- phasized. 0 ? 50 s/15 s pre-emphasis indicated. 1 ? 50 s/15 s pre-emphasis not indicated. 11.18 format detect status (12h) note: pcm, dts_ld, dts_cd and iec61937 are mutually exclusive. a ?1? indicated the condition was detected. pcm ? un-compressed pcm data was detected. iec61937 ? iec61937 data was detected. dts_ld ? dts_ld data was detected. dts_cd ? dts_cd data was detected. hd_cd ? hd_cd data was detected. dgtl_sil ? digital silence was detected: at least 2047 consecutive constant samp les of the same 24-bit audio data on both channels. 11.19 receiver error (13h) this register contains the aes3 receiver status bits. unmasked bits will go high on occurrence of the error, and will stay high until the register is read. reading th e register resets all bits to 0, unless the error source is still true. bits that are masked off in the receiver erro r mask register will always be 0 in this register. qcrc - q-subcode data crc error indicator. updated on q-subcode block boundaries 0 - no error. 1 - error. 76543210 pcm iec61937 dts_ld dts_cd hd_cd dgtl_sil reserved reserved 76543210 reserved qcrc ccrc unlock v conf bip par
ds692pp2 59 CS8422 ccrc - channel status block cyclic redundancy check bit. updated on cs block boundaries, valid only in pro mode. 0 - no error. 1 - error. unlock - receiver lock status when sourced by incoming aes3-compati ble data. updated on cs block boundaries. 0 - receiver locked. 1 - receiver out of lock. v - received aes3 validity bit status . updated on sub- frame boundaries. 0 - data is valid and is normally linear coded pcm audio. 1 - data is invalid, or may be valid compressed audio. conf - confidence bit. updated on sub-frame boundaries. 0 - no error. 1 - confidence error. the input data stream may be near error condition due to jitter degradation. bip - bi-phase error bit. updated on sub-frame boundaries. 0 - no error. 1 - bi-phase error. this indicates an error in the received bi-phase coding. par - parity bit. updated on sub-frame boundaries. 0 - no error. 1 - parity error. 11.20 interrupt status (14h) for all bits in this register, a ?1? means the associat ed interrupt condition has occurred at least once since the register was last read. a ?0? means the associated interrupt condition has not occurred since the last reading of the register. reading the register resets all bi ts to 0, unless the interrupt mode is set to level and the interrupt so urce is still true. status bits that are masked off in the associated mask register will always be ?0? in this register. pcch ? pc burst preamble change. indicates that the pc byte has changed from its previ ous value. if the iec61937 bit in the format detect status register goes high, it will cause a pcch interr upt even if the pc byte hasn?t changed since the last time the iec61937 bit went high. oslip - serial audio output port data slip interrupt when the serial audio output port is in slave mode, and olrck is asynchronous to the port data source, this bit will go high every time a data sample is dropped or repeated. see ?serial port clock operation? on page 25 for more information. 7654321 0 pcch oslip detc cch rerr qch fch src_unlock
60 ds692pp2 CS8422 detc - d to e c-buffer transfer interrupt. indicates the completion of a d to e c-buffer transfer. see ?channel status buffer management? on page 53. cch - c-data change. indicates that the current 10 bytes of channel status is different from th e previous 10 bytes. (5 bytes per channel) rerr - a receiver error has occurred. the receiver error register may be read to determine the nature of the error which caused the interrupt. qch ? a new block of q-subcode is available for reading. the data must be read wit hin 588 aes3 frames after the interrupt occurs to avoid co rruption of the data by the next block. fch ? format change goes high when the pcm, iec61937, dts_ld, dts_cd, or dgtl_sil bits in the format detect status register transition from 0 to 1. when these bits in t he format detect status regi ster transition from 1 to 0, an interrupt will no t be generated. src_unlock - src unlock condition. indicates that the s rc has lost the ability to output valid data 11.21 pll status (15h) rx_active - receiver active this bit is a level-signal version of the active bit in register 13h. isclk_active - isclk active 0 - there is no toggling on the isclk pin, or the fr equency of toggling is less than 36 khz on the isclk pin. 1 - there is toggling at a frequency of at least 1.536 mhz on the isclk pin. pll_lock - 0 - the pll has not achieved lock. 1 - the pll, driven by either an aes3 or isclk input, has achieved lock. 96khz ? indicates the freque ncy range of the sample rate of incoming aes3 data (fsi). if fsi 49 khz or fsi 120 khz, this bit will output a ?0?. if 60 khz fsi 98 khz, this bit will output a ?1?. other wise the output is indeterminate. 192khz ? indicates the frequency range of the sample rate of incoming aes3 data (fsi). if fsi 98 khz, this bit will output a ?0?. if fsi 120 khz, this bit will output a ?1?. ot herwise the output is indeterminate. 76543210 rx_active isclk active pll_lock 96khz 192khz reserved reserved reserved
ds692pp2 61 CS8422 11.22 receiver status (16h) cs_update - determines whether channel status register s and rcvr_rate are updated in the presence of a receiver error (register 14h). 0 - the receiver channel status registers and rcvr_rate are updated on each aes3 block boundary. 1 - the receiver channel status registers and rcvr_rate are updated on each aes3 block boundary if no biphase, confidence, parity, or crcc error has occurred during the reception of the channel status block. rcvr_rate - input sample rate represented in the ch annel status data of incoming aes3 data. 00 - reserved 01 - 32 khz 10 - 44.1 khz 11 - 48 khz rx_lock - aes3 receiver pll lock 0 - the pll has not achieved lock for more than 2 z preambles or aes3 input is not driving pll. 1 - goes high 2 z preambles after the pll has achieved lock when an aes3 input has been selected to drive the pll. blk_verr - block validity error. upda ted on detc boundaries 0 - the validity bit of the incoming aes3 data has remained low during the input of the last aes3 data block. 1 - the validity bit of inco ming aes3 data has gone hi gh at some point during the input of the last aes3 data block. blk_cerr - block confidence error. updated on detc boundaries 0 - the confidence bit associated with incoming aes3 data has remained high during the input of the last aes3 data block. 1 - the confidence bit associated with incoming aes3 data has gone low at least once during the input of the last aes3 data block. blk_berr - block biphase error. updated on detc boundaries 0 - there has be en no biphase error associated with incoming aes3 data duri ng the input of the last aes3 data block. 1 - there has been at least one biph ase error associated with incoming aes3 data during the input of the last aes3 data block. blk_perr - block parity error. updated on detc boundaries 0 - there has been no parity error associated with incoming aes3 data during the input of the last aes3 data block. 76543210 cs_update rcvr_rate1 rcvr_rate0 rx_lock blk_verr blk_cerr blk_berr blk_perr 0-------
62 ds692pp2 CS8422 1 - there has been at least one pa rity error associated with incoming aes3 data during the input of the last aes3 data block. 11.23 fs/xti ratio (17h - 18h) fs_xti[15:0] - 256*fs/xti, where fs is the sample rate of inco ming aes3-compatible data. the integer part of fs_xt[15:0] is represented in bits [15:10] in register 17h, and the fractional part is rep- resented in bits [9:0] of registers 17h and 18h; wit h a precision of 300 hz in fs and is updated approxi- mately every 2048/(xti fr equency). reading register 17h will caus e the value of 18h to freeze until register 18h is read. 11.24 q-channel subcode (19h - 22h) each byte is lsb first with respect to the 80 q-subcode bits q[79:0]. thus bit 7 of address 19h is q[0] while bit 0 of address 19h is q[7]. similarly bi t 0 of address 22h corresponds to q[79]. 11.25 channel status re gisters (23h - 2ch) each byte is msb first with respect to the 80 channel st atus bits. thus bit 0 of address 23h, ac0[0], is the location of the pro bit. fo r n = 0-79, channel status bi t n (per aes specif ication) is map ped to bit n mod 8 (remainder of n divided by 8) at address 23h+floor(n /8) (23h + integer result of n divided by 8 rounded down). for example, channel status bit 35 is mapped to bit 3 (35/8 = 4 remainder 3) of address 27h (23h + 4h). 76543210 fs_xt15 fs_xt14 fs_xt13 fs_xt12 fs_xt11 fs_xt10 fs_xt9 fs_xt8 fs_xt7 fs_xt6 fs_xt5 fs_xt4 fs_xt3 fs_xt2 fs_xt1 fs_xt0 76543210 control control control control address address address address track track track track track track track track index index index index index index index index minute minute minute minute minute minute minute minute second second second second second second second second frame frame frame frame frame frame frame frame zero zero zero zero zero zero zero zero abs minute abs minute abs minut e abs minute abs minute abs mi nute abs minute abs minute abs second abs second abs second abs second abs second abs second abs second abs second abs frame abs frame abs frame abs frame abs frame abs frame abs frame abs frame address channel status byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 23h channel a status byte 0 ac0[7] ac0[6] ac0[5] ac0[4] ac0[3] ac0[2] ac0[1] ac0[0] 24h channel a status byte 1 ac1[7] ac1[6] ac1[5] ac1[4] ac1[3] ac1[2] ac1[1] ac1[0] 25h channel a status byte 2 ac2[7] ac2[6] ac2[5] ac2[4] ac2[3] ac2[2] ac2[1] ac2[0] 26h channel a status byte 3 ac3[7] ac3[6] ac3[5] ac3[4] ac3[3] ac3[2] ac3[1] ac3[0] 27h channel a status byte 4 ac4[7] ac4[6] ac4[5] ac4[4] ac4[3] ac4[2] ac4[1] ac4[0] 28h channel b status byte 0 bc0[7] bc0[6] bc0[5] bc0[4] bc0[3] bc0[2] bc0[1] bc0[0] 29h channel b status byte 1 bc1[7] bc1[6] bc1[5] bc1[4] bc1[3] bc1[2] bc1[1] bc1[0] 2ah channel b status byte 2 bc2[7] bc2[6] bc2[5] bc2[4] bc2[3] bc2[2] bc2[1] bc2[0] 2bh channel b status byte 3 bc3[7] bc3[6] bc3[5] bc3[4] bc3[3] bc3[2] bc3[1] bc3[0] 2ch channel b status byte 4 bc4[7] bc4[6] bc4[5] bc4[4] bc4[3] bc4[2] bc4[1] bc4[0]
ds692pp2 63 CS8422 11.26 iec61937 pc/pd burs t preamble (2dh - 30h) address burst preamble byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2dh burst preamble pc byte 0 pc0[7] pc0[6] pc0[5] pc0[4] pc0[3] pc0[2] pc0[1] pc0[0] 2eh burst preamble pc byte 1 pc1[7] pc1[6] pc1[5] pc0[4] pc1[3] pc1[2] pc1[1] pc1[0] 2fh burst preamble pd byte 0 pd0[7] pd0[6] pd0[5] pc0[4] pd0[3] pd0[2] pd0[1] pd0[0] 30h burst preamble pd byte 1 pd1[7] pd1[6] pd1[5] pd1[4] pd1[3] pd1[2] pd1[1] pd1[0]
64 ds692pp2 CS8422 12.applications 12.1 reset, power down, and start-up when rst is low the CS8422 enters a low power mode, all internal states are reset, and the outputs are disabled. after rst transitions from low to high the part senses the resistor value on the configuration pins (ms_sel and saof) and sets the appropriate mode of operation. after the mode has been set (approxi- mately 4 s) the part is set to normal operation and all outputs are functional. 12.2 power supply, gr ounding, and pcb layout the CS8422 operates from a va = +3.3 v and vl = +1.8 v to +5.0 v supply. these supplies may be set independently. follow normal supply decoupling practices, see figure 7 and 8 for details. extensive use of power and ground pl anes, ground plane fill in unused areas, and su rface mount decoupling capacitors are recommended. decoupling capacitors sh ould be mounted on the same side of the board as the CS8422 to minimize inductance ef fects and all decoupling capacitors should be as close to the CS8422 as possible. the pin of the configuration resistors not connected to ms_sel and saof should be connect- ed as close as possible to vl or dgnd. 12.3 external receiver components the CS8422 aes3 receiver is designed to accept bo th the professional and co nsumer interfaces. the dig- ital audio specifications for prof essional use call for a balanced re ceiver, using xlr connectors, with 110 20% impedance. the xlr connector on the receiver should have female pins with a male shell. since the receiver has a very high input impedance, a 110 resistor should be placed across the receiver terminals to match the line impedance, as shown in figure 26 and figure 27 . although transformers are not required by the aes specification, they are strongly recommended. if some isolation is desired without the use of transformers, a 0.01 f capacitor should be placed in series with each input pin (rxp[3:0] and rxn[3:0]) as shown in figure 27 . however, if a transformer is not used, high frequency energy could be coupled into the receiver, causing degradation in analog performance. figure 26 and figure 27 show an optional (recommended) dc blocking capacitor (0.1 f to 0.47 f) in se- ries with the cable input. th is improves the robustness of the receiver, preventing the saturation of the trans- former, or any dc current flow, if a dc voltage is present on the cable. the circuit in figure 28 shows the input circuit for switching betwe en up to four single-ended signals in re- ceiver input mode 1 (analog sensitivity mode). if the application requires switching between a single-ended consumer interface and a differential interface, the cs842 2 must be in differential mode and the input circuit in figure 28 should be used for the single ended source. standards for the consumer interface call for an unbalanced circuit having a receiver impedance of 75 5%. the connector for the consumer interface is an rca phono socket. the circuit in figure 29 shows the input circuit for switching betw een up to four single-ended ttl or cmos signals, and should be used when the s/pdif receiver is in receiver input mode 2. if the application re- quires switching between a cmos or ttl source and a differential source, the CS8422 must be in differ- ential mode and the input circuit in figure 30 should be used for the single-ended digital source. if the application requires switching between a single ended source in mode 1, and a ttl or cmos source, the circuit in figure 30 should be used for the cmos/t tl source (no rxn connection is present in this case). when designing systems, it is im portant to avoid ground loops and dc current flowing down the shield of the cable that could result when boxes with different ground potentials are connected. generally, it is good practice to ground the shield to the chassis of the transmitting unit, and connect the shield through a capac- itor to chassis ground at the receiver. however, in some cases it is advantageous to have the ground of two
ds692pp2 65 CS8422 boxes held to the same potential, and the cable shield might be depended upon to make that electrical con- nection. generally, it is a good idea to provide the opti on of grounding or capacitively coupling the shield to the chassis. 12.3.1 attenuating input signals the input signals to the rx, rxp, and rxn pins in a ll modes of operation are limited to amplitudes equal to, or less than +3.3 v. in some cases it may be necessary to attenuate the input signal so the input to the device is within the valid operating range. figures 31 and 32 illustrate how this should be done for both sin- gle-ended and differential inputs. in both cases, e quations (1) and (2) must be satisfied simultaneously. 1 xlr 110 twisted pair 110 CS8422 rxp rxn * see text 1 xlr 110 CS8422 rxp0 rxn0 0.01 f 0.01 f *seetext 110 twisted pair figure 26. professional input circuit ? differential mode figure 27. transformerless professional input cir- cuit ? differential mode rx3 rx0 rx2 75 .01 f .01 f .01 f . . . 75 coax 75 75 75 coax 75 coax CS8422 rca phono rxp rxn CS8422 coax 75 75 0.01 f 0.01 f figure 28. s/pdif mux input ci rcuit ? single-ended receiver mode 1 single-ended input circuit ? differential mode rxp rxn CS8422 0.01 f 0.01 f ttl/cmos rx3 CS8422 ttl/cmos rx0 figure 29. s/pdif mux input circuit ? digital mode figure 30. ttl/cmos input circuit ? differential mode
66 ds692pp2 CS8422 12.3.2 isolating transformer requirements please refer to the application note an134: aes and spdif recomme nded transformers for resources on transformer selection 12.4 channel status buffer management 12.4.1 aes3 channel stat us (c) bit management the CS8422 contains sufficient ram to store the firs t 5 bytes of c data for both a and b channels (5 x 2 x 8 = 80 bits). the user may read from this buffer?s ram through the control port. the buffering scheme involves two bu ffers, named d and e, as shown in figure 33 . the msb of each byte represents the first bit in the serial c data stream. for example, the msb of byte 0 (which is at control port address 23h) is the consumer/professional bit for channel status block a. the first buffer (d) accepts incoming c da ta from the aes receiver. the 2nd buffer (e) acce pts entire blocks of data from the d buffer. the e buffer is also accessible from the control port, allowing reading of the first five bytes of c data. the complete c data may be obtained through the c pin in hardware mode and through one of the gpo pins in software mode. the c data is serially shifted out of the cs8 422 clocked by the rising and falling edges of olrck or vlrck. rx .01 f CS8422 agnd r1 r2 v in + - r2 = 247.5 v in r1 = 75 ? r2 75 coax (1) (2) figure 31. receiver input attenuation ? single-ended input 110 twisted pair CS8422 rxp rxn r in r in r agnd v in+ v in- (1) r = 726 v in+ - v in- (2) r in = 55 - r 2 figure 32. receiver input attenuation ? differential input
ds692pp2 67 CS8422 there are a number of co nditions that will inhibi t the buffer update. if the cs_update bit in ?receiver sta- tus (16h)? is set to ?0?, the only conditio n that will inhibit the update is pll phase unlock. if the cs_update bit in ?receiver status (16h)? is set to ?1?, a biphase, confidence, parity, or crc error will also inhibit the update. 12.4.2 accessing the e buffer the user can monitor the incoming data by reading the e buffer, which is mapped into the register space of the CS8422, through the control port. the user can configure the interrupt enable register to cause interrupts to occur whenever d to e buffer transfers occur. this allows determ ination of the allowable time periods to interact with the e buffer. also provided is a d to e inhibit bit in the ?receiver data control (04h)? register. this may be used whenever ?long? control port interactions are occurring or for debugging purposes. a flowchart for reading the e buffer is shown in figure 34 . since a d to e interrupt occurs just after reading, there is a substantial time interval until the next d to e transfer (approximately 192 frames worth of time). this is usually enough time to access the e da ta without having to inhibit the next transfer. from aes3 receiver e 8-bits 8-bits ab d received data buffer 5 words c data serial output control port registers 24 words figure 33. channel status data buffer structure d to e interrupt occurs optionally set d to e inhibit read e data if set, clear d to e inhibit return figure 34. flowchart for reading the e buffer
68 ds692pp2 CS8422 12.4.3 serial copy mana gement system (scms) in software mode, the CS8422 allows read access to all the channel status bits. for consumer mode scms compliance, the host microcontroller needs to read a nd interpret the category code, copy bit and l bit ap- propriately. in hardware mode, the scms protocol can be follo wed by using the c bit serial output pin. see ?channel status and user data handling? on page 34 for more details. 12.5 jitter attenuation figure 35 shows the jitter attenuation char acteristics of the CS8422 pll. the aes3 and iec60958-4 spec- ifications state a maximum of 2 db jitter gain. 10 2 10 3 10 4 10 5 10 6 10 7 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 jitter frequency (hz) external jitter attenuation (db) figure 35. CS8422 pll jitter attenuation characteristics
ds692pp2 69 CS8422 12.6 jitter tolerance figure 36 shows the receiver jitter tole rance template as illu strated in the aes3 and iec60958-4 specifi- cation. CS8422 devices have been tested to pass this template. 12.7 group delay the group delay introduced by the CS8422 depends on the type of interface selected, and input and output sample rates of the sample rate converter. the expression for the group delay through the CS8422 with the use of the sam- ple rate converter is shown below, where the interface de lay is 3 olrck periods in all modes except aes3 direct mode, in which it is 2 olrck periods. if the sample rate converter is not being used, then the approximate group delay will be equal to the interface delay . figure 36. jitter tolerance template totalgroupdelay 8.7 fsi ------- - 5 fso --------- interfacedelay ++ ?? ?? =
70 ds692pp2 CS8422 13.performance plots test conditions (unless otherwise sp ecified): measurement bandwidth is 20 hz to fso/2 hz (unweighted); va = vl = v_reg = 3.3 v; xti - xto = 24.576 mhz; input signal is a 0 dbfs 1 khz sine wave; data resolution is 24 bits; serial audio input and output ports set to sl ave; input and output clocks and data are asynchronous . -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 10k 90k 20k 30k 40k 50k 60k 70k 80k hz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2.5k 22.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k hz figure 37. wideband fft ? 0 dbfs 1 khz tone, 48 khz:48 khz figure 38. wideband fft ? 0dbfs 1khz tone, 44.1khz:192khz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2.5k 22.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k hz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2k 22k 4k 6k 8k 10k 12k 14k 16k 18k 20k hz figure 39. wideband fft ? 0 dbfs 1 khz tone, 44.1 khz:48 khz figure 40. wideband fft ? 0dbfs 1khz tone, 48khz:44.1khz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 5k 45k 10k 15k 20k 25k 30k 35k 40k hz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2.5k 22.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k hz figure 41. wideband fft ? 0 dbfs 1 khz tone, 48 khz:96 khz figure 42. wideband fft ? 0 dbfs 1 khz tone, 96 khz:48 khz
ds692pp2 71 CS8422 -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 5k 45k 10k 15k 20k 25k 30k 35k 40k hz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2.5k 22.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k hz figure 43. wideband fft ? 0 dbfs 1 khz tone, 192 khz:48 khz figure 44. wideband fft ? -60 dbfs 1 khz tone, 48 khz:96 khz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2.5k 22.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k hz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 10k 90k 20k 30k 40k 50k 60k 70k 80k hz figure 45. wideband fft ? -60dbfs 1khz tone, 48khz:48khz figure 46. wideband fft ? -60dbfs 1khz tone, 44.1khz:192khz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2.5k 22.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k hz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2k 22k 4k 6k 8k 10k 12k 14k 16k 18k 20k hz figure 47. wideband fft ? -60 dbfs 1 khz tone, 44.1 khz:48 khz figure 48. wideband fft ? -60 dbfs 1 khz tone, 48 khz:44.1 khz
72 ds692pp2 CS8422 -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2.5k 22.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k hz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2.5k 22.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k hz figure 49. wideband fft ? -60dbfs 1khz tone, 96khz:48khz figure 50. imd ? 10 khz and 11 khz -7 dbfs, 96 khz:48 khz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2.5k 22.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k hz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2k 22k 4k 6k 8k 10k 12k 14k 16k 18k 20k hz figure 51. wideband fft ? -60 dbfs 1 khz tone, 192 khz:48 khz figure 52. imd ? 10 khz and 11 khz -7 dbfs, 48 khz:44.1 khz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2.5k 22.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k hz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2.5k 22.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k hz figure 53. imd ? 10 khz and 11 khz -7 dbfs, 44.1 khz:48 khz figure 54. wideband fft ? 0 dbfs 20 khz tone, 44.1 khz:48 khz
ds692pp2 73 CS8422 -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 5k 45k 10k 15k 20k 25k 30k 35k 40k hz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 10k 90k 20k 30k 40k 50k 60k 70k 80k hz figure 55. wideband fft ? 0 dbfs 80 khz tone, 192 khz:192 khz figure 56. wideband fft ? 0 dbfs 20 khz tone, 48 khz:96 khz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2.5k 22.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k hz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2.5k 22.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k hz figure 57. wideband fft ? 0 dbfs 20 khz tone, 48 khz:48 khz figure 58. wideband fft ? 0 dbfs 20 khz tone, 96 khz:48 khz -200 +0 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 2k 22k 4k 6k 8k 10k 12k 14k 16k 18k 20k hz -2 00 +0 -1 90 -1 80 -1 70 -1 60 -1 50 -1 40 -1 30 -1 20 -1 10 -1 00 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 40k 180k 60k 80k 100k 120k 140k 160k hz t t figure 59. wideband fft ? 0 dbfs 20 khz tone, 48 khz:44.1 khz figure 60. thd+n vs. output sample rate ? 0dbfs 1khz tone, fsi=192khz
74 ds692pp2 CS8422 -2 00 +0 -1 90 -1 80 -1 70 -1 60 -1 50 -1 40 -1 30 -1 20 -1 10 -1 00 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 40k 180k 60k 80k 100k 120k 140k 160k hz -2 00 +0 -1 90 -1 80 -1 70 -1 60 -1 50 -1 40 -1 30 -1 20 -1 10 -1 00 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 40k 180k 60k 80k 100k 120k 140k 160k hz figure 61. thd+n vs. output sample rate ? 0 dbfs 1 khz tone, fsi = 48 khz figure 62. thd+n vs. output sample rate ? 0 dbfs 1 khz tone, fsi = 96 khz -2 00 +0 -1 90 -1 80 -1 70 -1 60 -1 50 -1 40 -1 30 -1 20 -1 10 -1 00 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 40k 180k 60k 80k 100k 120k 140k 160k hz -2 00 +0 -1 90 -1 80 -1 70 -1 60 -1 50 -1 40 -1 30 -1 20 -1 10 -1 00 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 40k 180k 60k 80k 100k 120k 140k 160k hz figure 63. thd+n vs. output sample rate ? 0dbfs 1khztone, fsi=44.1khz figure 64. dynamic range vs. output sample rate ? -60 dbfs 1 khz tone, fsi = 192 khz -2 00 +0 -1 90 -1 80 -1 70 -1 60 -1 50 -1 40 -1 30 -1 20 -1 10 -1 00 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 40k 180k 60k 80k 100k 120k 140k 160k hz -2 00 +0 -1 90 -1 80 -1 70 -1 60 -1 50 -1 40 -1 30 -1 20 -1 10 -1 00 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 40k 180k 60k 80k 100k 120k 140k 160k hz figure 65. thd+n vs. output sample rate ? 0 dbfs 1 khz tone, fsi = 32 khz figure 66. dynamic range vs. output sample rate ? -60dbfs 1khz tone, fsi=32khz
ds692pp2 75 CS8422 -2 00 +0 -1 90 -1 80 -1 70 -1 60 -1 50 -1 40 -1 30 -1 20 -1 10 -1 00 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 40k 180k 60k 80k 100k 120k 140k 160k hz -2 00 +0 -1 90 -1 80 -1 70 -1 60 -1 50 -1 40 -1 30 -1 20 -1 10 -1 00 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 40k 180k 60k 80k 100k 120k 140k 160k hz figure 67. dynamic range vs. output sample rate ? -60 dbfs 1 khz tone, fsi = 96 khz figure 68. dynamic range vs. output sample rate ? -60 dbfs 1 khz tone, fsi = 44.1 khz -1 40 +5 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 -1 00 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 +0 d b f s 10k 60k 20k 30k 40k 50k hz tt t tt t -0 .2 +0 -0.19 -0.18 -0.17 -0.16 -0.15 -0.14 -0.13 -0.12 -0.11 -0 .1 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 d b f s 0 25k 5k 10k 15k 20k hz figure 69. frequency response ? 0 dbfs input figure 70. passband ripple ? 192 khz:48 khz 192 khz : 32 khz 192 khz : 48 khz 192 khz : 96 khz -2 00 +0 -1 90 -1 80 -1 70 -1 60 -1 50 -1 40 -1 30 -1 20 -1 10 -1 00 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 40k 180k 60k 80k 100k 120k 140k 160k hz -1 40 +0 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 -1 00 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b f s -140 +0 -120 -100 -80 -60 -40 -20 dbfs figure 71. dynamic range vs. output sample rate ? -60 dbfs 1 khz tone, fsi = 48 khz figure 72. linearity error ? 0 to -140 dbfs input, 200 hz tone, 48 khz:48 khz
76 ds692pp2 CS8422 -1 40 +0 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 -1 00 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b f s -14 0 +0 -120 -100 -80 -60 -40 -20 db fs -1 40 +0 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 -1 00 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b f s -140 +0 -120 -100 -80 -60 -40 -20 dbfs figure 73. linearity error ? 0 to -140 dbfs input, 200 hz tone, 48 khz:44.1 khz figure 74. linearity error ? 0 to -140 dbfs input, 200 hz tone, 48 khz:96 khz -1 40 +0 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 -1 00 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b f s -140 +0 -120 -100 -80 -60 -40 -20 dbfs -1 40 +0 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 -1 00 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b f s -14 0 +0 -120 -100 -80 -60 -40 -20 db fs figure 75. linearity error ? 0 to -140 dbfs input, 200 hz tone, 96 khz:48 khz figure 76. linearity error ? 0 to -140 dbfs input, 200 hz tone, 44.1 khz:192 khz -1 40 +0 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 -1 00 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b f s -140 +0 -120 -100 -80 -60 -40 -20 dbfs -1 40 +0 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 -1 00 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b f s -140 +0 -120 -100 -80 -60 -40 -20 dbfs figure 77. linearity error ? 0 to -140 dbfs input, 200 hz tone, 44.1 khz:48 khz figure 78. linearity error ? 0to-140dbfs input, 200hztone, 192khz:44.1khz
ds692pp2 77 CS8422 -1 80 -1 00 -1 75 -1 70 -1 65 -1 60 -1 55 -1 50 -1 45 -1 40 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 d b f s -140 +0 -120 -100 -80 -60 -40 -20 dbfs -1 80 -1 00 -1 75 -1 70 -1 65 -1 60 -1 55 -1 50 -1 45 -1 40 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 d b f s -140 +0 -120 -100 -80 -60 -40 -20 dbfs figure 79. thd+n vs. input amplitude ? 1 khz tone, 48 khz:44.1 khz figure 80. thd+n vs. input amplitude ? 1 khz tone, 48 khz:96 khz -1 80 -1 00 -1 75 -1 70 -1 65 -1 60 -1 55 -1 50 -1 45 -1 40 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 d b f s -140 +0 -120 -100 -80 -60 -40 -20 dbfs -1 80 -1 00 -1 75 -1 70 -1 65 -1 60 -1 55 -1 50 -1 45 -1 40 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 d b f s -140 +0 -120 -100 -80 -60 -40 -20 dbfs figure 81. thd+n vs. input amplitude ? 1 khz tone, 96 khz:48 khz figure 82. thd+n vs. input amplitude ? 1 khz tone, 44.1 khz:192 khz -1 80 -1 00 -1 75 -1 70 -1 65 -1 60 -1 55 -1 50 -1 45 -1 40 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 d b f s -14 0 +0 -120 -100 -80 -60 -40 -20 db fs -1 80 -1 00 -1 75 -1 70 -1 65 -1 60 -1 55 -1 50 -1 45 -1 40 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 d b f s -14 0 +0 -120 -100 -80 -60 -40 -20 db fs figure 83. thd+n vs. input amplitude ? 1khz tone, 44.1khz:48khz figure 84. thd+n vs. input amplitude ? 1khz tone, 192khz:48khz
78 ds692pp2 CS8422 -1 80 -1 00 -1 75 -1 70 -1 65 -1 60 -1 55 -1 50 -1 45 -1 40 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 d b f s 0 20k 2k 4k 6k 8k 10k 12k 14k 16k 18k hz -1 80 -1 00 -1 75 -1 70 -1 65 -1 60 -1 55 -1 50 -1 45 -1 40 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 d b f s 0 20k 2k 4k 6k 8k 10k 12k 14k 16k 18k hz figure 85. thd+n vs. input frequency ? 0 dbfs, 48 khz:44.1 khz figure 86. thd+n vs. input frequency ? 0 dbfs, 48 khz:96 khz -1 80 -1 00 -1 75 -1 70 -1 65 -1 60 -1 55 -1 50 -1 45 -1 40 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 d b f s 0 20k 2k 4k 6k 8k 10k 12k 14k 16k 18k hz -1 80 -1 00 -1 75 -1 70 -1 65 -1 60 -1 55 -1 50 -1 45 -1 40 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 d b f s 0 20k 2k 4k 6k 8k 10k 12k 14k 16k 18k hz figure 87. thd+n vs. input frequency ? 0 dbfs, 44.1 khz:48 khz figure 88. thd+n vs. input frequency ? 0 dbfs, 96 khz:48 khz -1 80 -1 00 -1 75 -1 70 -1 65 -1 60 -1 55 -1 50 -1 45 -1 40 -1 35 -1 30 -1 25 -1 20 -1 15 -1 10 -1 05 d b f s 0 20k 2k 4k 6k 8k 10k 12k 14k 16k 18k hz figure 89. total power supply current vs. differential mode receiver input sample frequency
ds692pp2 79 CS8422 14.package dimensions notes: 1. dimensioning and tolerance per asme y 14.5m-1995. 2. dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip 15.thermal characteristics and specifications notes: 1. ja is specified according to jedec sp ecifications for multi-layer pcbs. inches millimeters note dim min nom max min nom max a----0.0394----1.00 1 a1 0.0000 -- 0.0020 0.00 -- 0.05 1 b 0.0079 0.0098 0.0118 0.20 0.25 0.30 1 , 2 d 0.1969 bsc 5.00 bsc 1 d2 0.1437 0.1457 0.1476 3.65 3.70 3.75 1 e 0.1969 bsc 5.00 bsc 1 e2 0.1437 0.1457 0.1476 3.65 3.70 3.75 1 e 0.0197 bsc 0.50 bsc 1 l 0.0118 0.0157 0.0197 0.30 0.40 0.50 1 jedec #: mo-220 controlling dimensio n is millimeters. parameters symbol min typ max units package thermal resistance (note 1) ja -38-c/watt allowable junction temperature - - 125 c side view a1 bottom view top view a pin #1 corner d e d2 l b e pin #1 corner e2 32l qfn (5 x 5 mm body) package drawing
80 ds692pp2 CS8422 16.ordering information 17.references 1. audio engineering society aes3-2003: ?aes standard for digital audio - digital input-output interfacing - serial transmission format for two-channel linearly represented digital audio data,? september 2003. 2. audio engineering society aes-12id-2006: ?aes information document for digital audio measurements - jitter performance specifications,? may 2007. 3. philips semiconductor, ? the i2c-bus specification: version 2 ,? dec. 1998. http://www.semiconductors.philips.com product description package pb-free grade temp range container order# CS8422 24-bit, asynchronous sample rate converter with integrated digital interface receiver qfn yes commercial -40 to +85c rail CS8422-cnz tape and reel CS8422-cnzr automotive -40 to +105c rail CS8422-dnz tape and reel CS8422-dnzr cdb8422 evaluation board for CS8422 - yes - - - cdb8422
ds692pp2 81 CS8422 18.revision history release changes pp1 added interchannel phase deviation to performance specifications - sample rate converter table added gain error to performance specifications - sample rate converter table added 32 khz:48 khz dynamic range to performance specifications - sample rate converter table updated (note 2) in performance specifications - sample rate converter table updated values in dc electrical characteristics table changed (note 3) and (note 4) in dc electrical characteristics table updated rmck jitter specification in switching specifications table changed (note 9) in switching specifications table moved sdin/tdm_in setup and hold times in switching specifications table changed master mode non-tdm i/osclk minimum frequency in switching specifications table changed t srs value in switching characteristics - control port - spi mode changed t irs value in switching characteristics - control port - i2c mode fixed calculation error in section 5.1.5.2 tdm slave mode added note to section 11.9 recovered master clock ratio control & misc. (09h) added section 12.6 jitter tolerance added section 13. performance plots added section 17. references updated vih minimum specification in digital interface specifications table updated vil maximum specification in digital interface specifications table updated input hysteresis specification in digital interface specifications table added (note 6) to digital interface specifications table removed vih maximum specification in digital interface specifications table removed vil minimum specification in digital interface specifications table pp2 updated package dimensions in section 14. package dimensions
82 ds692pp2 CS8422 contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com . important notice ?preliminary? product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its sub- sidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of re levant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and condit ions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnif ication, and limitation of liability. no responsibility is assu med by cirrus for the use of this informa- tion, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or ot her rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, m ask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herei n and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of c irrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resal e. certain applications using semi conductor products may involve po tential risks of death, perso nal injury, or severe prop- erty or environmental damage (? critical applications?). cirrus products are not designed, authorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life su pport products or other crit- ical applications. inclus ion of cirrus products in such appl ications is understood to be full y at the customer?s risk and cir- rus disclaims and makes no warranty, expres s, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or custom- er?s customer uses or permits the use of cirrus products in cr itical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any a nd all liability, including at- torneys? fees and costs, that may result fr om or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. ac-3 is a registered trademark of dolby laboratories, inc. dts is a registered trademark of digital theater systems, inc. i2c is a registered trademark of philips semiconductor. spi is a trademark of motorola, inc.

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